loogg / agile_modbus Goto Github PK
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License: Apache License 2.0
Home Page: https://github.loogg.cn/agile_modbus/
License: Apache License 2.0
case AGILE_MODBUS_FC_WRITE_SINGLE_COIL: {
//! warning: comparison is always false due to limited range of data type [-Wtype-limits]
#if 0
if (address > 0xFFFF) {
exception_code = AGILE_MODBUS_EXCEPTION_ILLEGAL_DATA_ADDRESS;
break;
}
#endif
int data = (req[offset + 3] << 8) + req[offset + 4];
if (data == 0xFF00 || data == 0x0)
data = data ? 1 : 0;
else {
exception_code = AGILE_MODBUS_EXCEPTION_ILLEGAL_DATA_VALUE;
break;
}
slave_info.buf = (uint8_t *)&data;
rsp_length = req_length;
if (ctx->send_bufsz < (int)(rsp_length + ctx->backend->checksum_length)) {
exception_code = AGILE_MODBUS_EXCEPTION_NEGATIVE_ACKNOWLEDGE;
break;
}
memcpy(rsp, req, req_length);
} break;
slave_info.buf = (uint8_t *)&data;
volatile struct agile_modbus_slave_info *debug_slave_info = {0};
debug_slave_info = &slave_info;
slave_info.buf = (uint8_t *)&data;
agile_modbus_receive_msg_judge是怎么回事
看了源码,对从机来说,有点冗余,尤其是接口那里,当寄存器大于一定的值之后,这个可能就不适用了
我看了一下从机的代码,一方面对于map_buf数组长度有限制,这个还不是主要问题(因为Modbus协议本身就有定义每次最多只允许操作124个寄存器).
但是不管是读取寄存器还是写入寄存器,你都需要把该字段的所有寄存器全部读取一次,这样的操作是否有冗余,这样的操作是为什么?理论上读取寄存器我们只需要读取对应的寄存器就好了,不需要把整个字段的寄存器都读取出来。写入寄存器的时候也不需要读取寄存器啊!所以这一块没有特别搞懂?是否可以优化。
按照库中校验函数,高位在后地位在前,agile_modbus_rtu_check_integrity中crc_received的值的算法是颠倒的
`
static int agile_modbus_rtu_check_integrity(agile_modbus_t *ctx, uint8_t *msg, const int msg_length)
{
uint16_t crc_calculated;
uint16_t crc_received;
crc_calculated = agile_modbus_rtu_crc16(msg, msg_length - 2);
crc_received = (msg[msg_length - 2] << 8) | msg[msg_length - 1];/*该处应修改为crc_received = (msg[msg_length - 1] << 8) | msg[msg_length - 2];*/
//mrd_log_printf(MRD_DEBUG,"crc_calculated = %d,crc_received=%d\n",crc_calculated,crc_received);
/* Check CRC of msg */
if (crc_calculated == crc_received)
return msg_length;
return -1;
}
`
可以用requst packet推出rsp packet len, 这样提高分包效率
希望能加一个接口,可以无需主机请求,主动推送对应的数据。
接口只需要传入功能码,起始地址,结束地址即可。
看了一下,目前在 rt-thread 中使用,还需要改不少地方,不知道您什么是否能够适配完?
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