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spsc_queue's Introduction

SPSC_Queue

A single producer single consumer lock-free queue C++ template for ultimate low latency, which can be used in multithread conmunication as well as in shared memory IPC under Linux.

The latency of communication of a 10-200B message is within 50-100 ns between two cpu cores on the same node. Sender and receiver don't need to copy a single byte of the msg, that is, a msg is allocated in the queue memory and set by sender, then read directly by the receiver in another thread/process.

This Library mainly contains 4 C++ templates, 2 for single typed queue and 2 for variant typed queue:

SPSCQueue.h

An atomic(crash safe when used in shared-memory IPC) single typed queue template.

SPSCQueueOPT.h

An optimized implementation of SPSCQueue, in which each msg has an additional bool header and write_idx and read_idx are not shared between threads. Note that Push() and Pop() operation are not atomic so it should not be used in IPC.

SPSCVarQueue.h

An atomic(crash safe when used in shared-memory IPC) general purpose variant typed queue template, with a header before each msg. This queue is used in TCPSHM: a connection-oriented persistent message queue framework based on TCP or SHM .

SPSCVarQueueOPT.h

An optimized implementation of SPSCVarQueue, in which reader doens't need to read write_idx so latency is reduced when new msg comes. Note that SPSCVarQueueOPT is not atomic.

Test

shmq_recv.cc/shmq_send.cc

A shared memory IPC example for testing SPSCQueue/SPSCQueueOPT.

multhread_q.cc

A multi-thread example for testing SPSCQueue/SPSCQueueOPT.

multhread_varq.cc

A multi-thread example for testing SPSCVarQueue/SPSCVarQueueOPT

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spsc_queue's Issues

消费者感知消息问题

你好, 我测试了SPSCQueue.h的代码,发现前CNT条消息,收不到?要写满CNT条消息后,消费者才能读取到第1条消息

Target Architecture (armv8 compatibility)?

Hi,

I am trying to figure out the portability / correctness of SPSCQueue.h on different architetures, especially armv8.

For this, I am mostly going by https://www.kernel.org/doc/Documentation/memory-barriers.txt
My understanding is that both pop / push obviously need to happen in correct order / atomic.

I am familiar with
__asm__ volatile("" ::: "memory")
to enforce a compiler level barrier and
__asm__ volatile ("mfence" ::: "memory")
to actually enforce a cpu barrier at runtime.

This should boil down to _mm_mfence (x86) or __mf (arm).

It's not clear to me how, e.g.
asm volatile("" : "=m"(data) : "m"(read_idx) :); // memory fence
enforce a barrier at runtime.

Is this the case because x86 has a more or less strict memory ordering, and the ops are atomic (are they?)? Or is a full memory fence simply not needed in this case.

Also: How portable is this to architectures with weak memory ordering, e.g. to armv8?
Would std::atomic_thread_fence be needed as replacement? I see you used that at the beginning before replacing it with the asm instructions.

Many thanks for your efforts! :-)

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