Error (169282): There are 1408 IO output pads in the design, but only 458 IO output pad locations available on the device.
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Can you please help us with these errors? Got these errors while compiling keyExpanison.v

1-In AES_tb.v , what is the purpose of checking the LEDS?. Why are we turning on and off the enable

2-What if comparison fails between encrypted and expected results.What will be the result and why?

hello sir,
I wanted to know how we implement our code on DE1SOC board. Is there any coding for that? Can you help with this one

We tried compiling the code of addRoundKey and same error occurred. Kindly guide us about this error. Should we select some different device or should we make changing in the code. Kindly help us with this error

Thankyou so much for your help. This issue was resolved. You will be remembered in our prayers

Can you explain what is happening in these lines? It is a part of AES.v file . Explanation needed