Extended Hamming Encoder Decoder implementation in VHDL

Implemention of Hamming code of codeword length of 8 bits, were data represent 4 bits and parity check are 4 bits added. Hamming (8,4) will be implemented at transmitter through finding generator matrix and multiplied by data input from Linear Feedback Shift Register (LFSR) result in transmitted 8 bits. At receiver we find parity check matrix ad then multiplied with inverse of codeword transmitted giving 4 bits output indicating and detecting error transmitted and correcting only 1 bit of error by locating its place index inside the 8 bits. If the result of this multiplication is “000” then the bits transmitted without error. Else there is error. At last comparing transmitted with manual error input acting as channel noise versus received and decode the right data transmitted. Manual error at normal and worst cases when noise invert 1 bit in parity. Error of more than 1 bit is not applicable since system is only suitable only for Bit Error Rate BER that is guarantee channel noise don’t invert more than 1 bit. It is called Extended Hamming code since the fourth added parity bit is to check double errors or more happened, it should be “0” when there is no error and vice versa.