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7-taskbar-tweaker

Windows Taskbar Customization Tool

aaad

acfun-video-download

一个用于AcFun的视频下载器。

advanced-uvm-second_edition

Code for the second edition of Advanced UVM.

amiq_apb

SystemVerilog VIP for AMBA APB protocol

amiq_blog

Code snippets from articles published on www.amiq.com/consulting/blog

amiq_fifo

Functional Coverage Patterns for FIFO

amiq_i2c

Verification Component for I2C protocol

arduino_freertos

FreeRtos tutorial examples on arduino

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

autosva

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi_dma

General Purpose AXI Direct Memory Access

azadi-soc

Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

bare_metal_cpp

Generated site from https://github.com/arobenko/bare_metal_cpp_src. Browse to https://arobenko.github.io/bare_metal_cpp/.

bare_metal_cpp_src

Source of the "Practical Guide to Bare Metal C++" free e-book

basic_uvmc

A simple testbench with two refmods using UVM Connect

bitfield

:cake: bit field diagram renderer

book-1

books

book collection

boris

Python script to manage Questa/Modelsim simulations

chipyard

chiselverify

A dynamic verification library for Chisel.

cluelib

A generic class library in SystemVerilog

computer-networking-a-top-down-approach-v7-material

Computer netweorking course

containers

Bitnami container images

core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cores-swerv-support-package

Processor support packages

cores-veer

VeeR EH1 core