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uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

uvm-verification-ip-for-switch

A complete UVM verification IP for simple switch (router)

uvm-verification-testbench-for-simplebus

uvm_agent_gen

UVM Agent Generator

uvm_axi

uvm AXI BFM(bus functional model)

uvm_book_examples

UVM Book Examples - A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition

uvm_codes

uvm_course

All about UVM

uvm_example

Example SystemVerilog UVM Environment

uvm_reg_to_ipxact

uvm_tb_cross_bar

SystemVerilog UVM testbench example

uvm_teatbench_for_rom

Complete UVM TestBench for verification of ROM

uvm_testbench_for_single_port_ram

A complete UVM TB for verification of single port 64KB RAM

uvm_testbench_gen

Novel GUI Based UVM Testbench Template Builder

uvm_verification

Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence

uvmm

It is the UVM library

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

uvvm

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

verilog-hdl

things about Verilog hardware description language

verilog-hdl_solution-manual

Solution manual for Verilog HDL a Guide to Digital Design and Synthesis by Samir Palnitkar

videoplayer

vscode-systemverilog

SystemVerilog support in VS Code

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

xrdp

xrdp: an open source RDP server