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Nasir Khan's Projects

slang icon slang

SystemVerilog compiler and language services

smtdv icon smtdv

make your verilog DUT test more smart

stuxnet icon stuxnet

Open-source decompile of Stuxnet/myRTUs

sv-1800-2012 icon sv-1800-2012

IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definition for VS Code

sv-tests icon sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

sva_traces icon sva_traces

Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors

svaunit icon svaunit

SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)

swerv_eh1 icon swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

ustc-rvsoc icon ustc-rvsoc

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。

uvm icon uvm

Standard Universal Verification Methodology

uvm-2 icon uvm-2

Mirror of the Universal Verification Methodology from sourceforge

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