Sorry this is in English.
This is what happens when I try 'make sint' in T01-setbit:
[~/open-fpga-verilog-tutorial/tutorial/ICESTICK/T01-setbit]$ make sint
-- Sintesis
yosys -p "synth_ice40 -blif setbit.blif" setbit.v
/----------------------------------------------------------------------------
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2015 Clifford Wolf [email protected] |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
----------------------------------------------------------------------------/
Yosys 0.5 (git sha1 c3c9fbf, gcc 5.2.1-15 -O2 -fstack-protector-strong -fPIC -Os)
-- Parsing setbit.v' using frontend
verilog' --
- Executing Verilog-2005 frontend.
Parsing Verilog input from setbit.v' to AST representation. Generating RTLIL representation for module
\setbit'.
Successfully finished Verilog frontend.
-- Running command `synth_ice40 -blif setbit.blif' --
ERROR: No such command: synth_ice40 (type 'help' for a command overview)
Makefile:41: recipe for target 'setbit.bin' failed
make: *** [setbit.bin] Error 1
Looking through the documentation for yosys, it appears that there is a 'synth' command and a 'synth_xilinx' but no 'synth_ice40'. Did I miss something?
Thanks,
Matt