Hello Dr. Jiao! We have completed the linux porting, but now there is no wifi ssid and the quadrature calibration fails. Please tell me what may be the reason

thank you

Getting the following error while running the TCL script:

INFO: [BD 41-434] Could not find an IP with XCI file by name: system_axi_hdmi_core_0 
can't read "auto_set_param_list": no such variable
ERROR: [BD 41-1273] Error running init TCL procedure: can't read "auto_set_param_list": no such variable
    adi_auto_assign_device_spec Line 18

hello, excuse me , how should I use the TSF between two boards(one in AP station,one in client station )?Can you give me some help?

Please check this. There is no files in /zc706_fmcs2/ip/openofdm_rx after the make step.

Thank.

Jinsan Ko

I am getting these critical warnings:

[BD 41-1629] </sys_ps7/S_AXI_ACP/ACP_M_AXI_GP0> is excluded from all addressable master spaces.
[BD 41-1629] </sys_ps7/S_AXI_ACP/ACP_QSPI_LINEAR> is excluded from all addressable master spaces.
[BD 41-1629] </sys_ps7/S_AXI_ACP/ACP_IOP> is excluded from all addressable master spaces.
[BD 41-1629] </sys_ps7/S_AXI_ACP/ACP_M_AXI_GP1> is excluded from all addressable master spaces.

Not sure why these addresses are excluded? Is there any way to fix these warnings?

Thanks a lot,
Francesco

Hello Dr. Jiao, can you tell me whether openwifi can work in pcf mode?

I am trying to get openwifi-hw running with a new Vivado version (2021.1 on Ubuntu 18).

However, source ./openofdm_rx.tcl from the script package_ip_openofdm_rx.tcl gives this error:
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:zc706:part0:1.2. The project's board_part property was not set, but the project's part property was set to xc7z045ffg900-2. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.

The problem is the following line:
create_project ${project_name} ./${project_name} -part xc7z045ffg900-2

I think it might be because this part is not available in Vivado webpack. Do You think we should make this "xc7z045ffg900-2" so that the correct FPGA for each board is selected? I am using antsdr, so a xc7z020 should be used.

Hi,

I was going through the design code and was wondering what is the purpose of the mixer in the DDC module in rx_intf. After you decimate the 40MHz band signal coming from the ADC to 20MHz, why do you further need a mixer? The signal should be centered to baseband, right?

By looking at the sdr.c driver, it seems that you are setting the mixer configurations to two different values for TX and RX chains. May I ask why and what do these configs represent?

    priv->rx_intf_cfg = RX_INTF_BW_20MHZ_AT_0MHZ_ANT0;
    priv->tx_intf_cfg = TX_INTF_BW_20MHZ_AT_N_10MHZ_ANT1;

Last question -- by looking at src.c, I can see that you do not set the RF bandwidth to 40MHz manually -- may I ask why? Is it the default value for AD9361, and where can I check that this is actually the case?

Thanks a lot!

I'd really like to see support for open hardware SDRs like the HackRF One (or the LimeSDR projects).

As far as I know, the HackRF One uses a CPLD instead of a FPGA. Unfortunaletely, I've no experience with FPGAs or alike therefore I would like know whether porting openwifi to the HackRF One is possible and what steps might be required for the port.

Some information about the HackRF One:

• hardware specifications: https://github.com/mossmann/hackrf/wiki/HackRF-One
  CPLD
• hardware components: https://github.com/mossmann/hackrf/wiki/Hardware-Components
• CPLD firmware: https://github.com/mossmann/hackrf/tree/master/firmware/cpld

I'd be happy to help with whatever I can (e.g. testing).

Hi, recently I began to experience problems with the build of the openwifi-hw project, I use vivado 2018.3 build configuration zc706 fmcs2, this problem did not arise before, I tried several times to download the repository but it didn’t help, can you tell me what this problem might be related to?

[IP_Flow 19-3188] Error occurred while initializing 'system_sys_audio_clkgen_0'
Tcl error in update procedure while setting value 'MMCM' on the parameter 'PRIMITIVE'. FALSE

[IP_Flow 19-3428] Failed to create Customization object system_sys_audio_clkgen_0
[BD 41-1712] Create IP failed with errors
[BD 41-595] Failed to add BD cell <sys_audio_clkgen>
[IP_Flow 19-973] Failed to create IP instance 'system_sys_audio_clkgen_0'. Error during customization.

hello,
when I run openwifi.tcl,
cd /home/zhangpeng/desktop/openwifi-hw-master/boards/zc706_fmcs2
source ./openwifi.tcl

set fd [open "openwifi_rev.coe" w]

fatal: 不是 git 仓库（或者直至挂载点 / 的任何父目录）
停止在文件系统边界（未设置 GIT_DISCOVERY_ACROSS_FILESYSTEM）。
while executing
"exec git log -1 --pretty=%h"
invoked from within
"set HASHCODE [exec git log -1 --pretty=%h]"
(file "./openwifi.tcl" line 23)

Is this a Git problem? I am not familiar with git

Looking forward your reply

Hi,
In this step:
Open Block Design
Tools --> Report --> Report IP Status

I get the following error:

 [BD 41-1273] Error running post_config_ip TCL procedure: unexpected "," outside function argument list
    ::xilinx.com_ip_zynq_ultra_ps_e_3.2::post_config_ip Line 47

Any idea of how to solve it?

best regards

0. Could you send email to [email protected] to introduce your self?

1. Our image is used directly or you build your own image?

2. What is your own modification?

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision

4. Board/hardware type

5. WiFi channel number

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

Hello,

I am currently trying to extract the samples after the CFO correction out of Verilog to the processor and to print them to a console or similar. I am using the Zedboard with AD-FMCOMMS3.
My first question is, if there is already an easy way to extract those samples? Maybe there is already an interface which I overlooked?

If there is not an interface, what would you consider the easiest way to accomplish my goal?
In Vivado I already created the outputs for everything and connected an AXI DMA:

You can see that I created tdata_rotated, tvalid_rotated and so on. However, I struggle to find an easy way to read the registers on the AXI DMA with C.

I also thought about connecting the newly created pins to the already existing AXI DMA and to change the sdr.c accordingly. But before I try this or more, I would like to hear your opinion about my questions.

Hi
Its really great.
I want to know that how can i simulate these designs?
Regards
hyanki

0. Could you send email to [email protected] to introduce your self?

1. Our image is used directly or you build your own image?

2. What is your own modification?

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision

4. Board/hardware type

5. WiFi channel number

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

When I clone master branch directly, and following the README to use ip_repo_gen.tcl to generate project will report error.

But if I clone master branch user --recursive parameter, the project will be built successfully.

I think the matter is the variable $argv must be cleared before source openofdm_rx.tcl.
./get_ip_openofdm_rx.sh link to branch dot11zynq made a mistake.

This is my vivado log.

source ip_repo_gen.tcl
# exec rm -rf ip_repo
# exec mkdir ip_repo
# exec cp ../../ip/board_def.v ./ip_repo/ -f
# set  fd  [open  "./ip_repo/openwifi_hw_git_rev.v"  w]
# set HASHCODE [exec ../../get_git_rev.sh]
# puts $fd "`define OPENWIFI_HW_GIT_REV (32'h$HASHCODE)"
# close $fd
# set has_side_ch 1 
# set  fd  [open  "./ip_repo/has_side_ch_flag.v"  w]
# if {$has_side_ch > 0} {
#   puts $fd "`define HAS_SIDE_CH 1"
# } else {
#   puts $fd "`define NO_SIDE_CH 1"
# }
# close $fd
# set small_fpga 1
# set  fd  [open  "./ip_repo/fpga_scale.v"  w]
# if {$small_fpga == 1} {
#   puts $fd "`define SIDE_CH_LESS_BRAM 1"
# }
# close $fd
# set NUM_CLK_PER_US 100
# set  fd  [open  "./ip_repo/clock_speed.v"  w]
# puts $fd "`define NUM_CLK_PER_US $NUM_CLK_PER_US"
# if {$small_fpga == 1} {
#   puts $fd "`define SMALL_FPGA 1"
# }
# close $fd
# set grounded_rf_port 0
# set  fd  [open  "./ip_repo/spi_command.v"  w]
# if {$grounded_rf_port == 1} {
#   puts $fd "`define SPI_HIGH 24'hC22001"
#   puts $fd "`define SPI_LOW 24'hC02001"
# } else {
#   puts $fd "`define SPI_HIGH 24'h088A01"
#   puts $fd "`define SPI_LOW 24'h008A01"
# }
# close $fd
# set ultra_scale_flag 0
# set part_string xc7z020clg484-1
# set argc 3
# set ip_name openofdm_rx
# exec rm -rf project_1
# set current_dir [pwd]
# set argv [list $ultra_scale_flag $current_dir/../../ip/$ip_name $current_dir/ip_repo/$ip_name]
# source ../package_ip_openofdm_rx.tcl
## set ultra_scale_flag [lindex $argv 0]
## set src_dir [lindex $argv 1]
## set ip_dir [lindex $argv 2]
## exec rm -rf project_1
## exec rm -rf $ip_dir
## set current_dir [pwd]
## cd $src_dir/
## if {$ultra_scale_flag > 0} {
##     exec rm -rf openofdm_rx_ultra_scale
##     source ./openofdm_rx_ultra_scale.tcl
## } else {
##     exec rm -rf openofdm_rx
##     source ./openofdm_rx.tcl
## }
### set ARGUMENT1 [lindex $argv 0]
### set ARGUMENT2 [lindex $argv 1]
### set ARGUMENT3 [lindex $argv 2]
### set ARGUMENT4 [lindex $argv 3]
### set ARGUMENT5 [lindex $argv 4]
### set ARGUMENT6 [lindex $argv 5]
### set ARGUMENT7 [lindex $argv 6]
### if {$ARGUMENT1 eq ""} {
###   set BOARD_NAME zed_fmcs2
### } else {
###   set BOARD_NAME $ARGUMENT1
### }
### if {$ARGUMENT2 eq ""} {
###   set NUM_CLK_PER_US 100
### } else {
###   set NUM_CLK_PER_US $ARGUMENT2
### }
### source ./parse_board_name.tcl
#### if {$BOARD_NAME=="zed_fmcs2"} {
####    set ultra_scale_flag 0
####    set part_string xc7z020clg484-1
####    set fpga_size_flag 0
#### } elseif {$BOARD_NAME=="zcu102_fmcs2"} {
####    set ultra_scale_flag 1
####    set part_string xczu9eg-ffvb1156-2-e
####    set fpga_size_flag 1
#### } elseif {$BOARD_NAME=="zc706_fmcs2"} {
####    set ultra_scale_flag 0
####    set part_string xc7z045ffg900-2
####    set fpga_size_flag 1
#### } elseif {$BOARD_NAME=="zc702_fmcs2"} {
####    set ultra_scale_flag 0
####    set part_string xc7z020clg484-1
####    set fpga_size_flag 0
#### } elseif {$BOARD_NAME=="antsdr"} {
####    set ultra_scale_flag 0
####    set part_string xc7z020clg400-1
####    set fpga_size_flag 0
#### } elseif {$BOARD_NAME=="adrv9361z7035"} {
####    set ultra_scale_flag 0
####    set part_string xc7z035ifbg676-2L
####    set fpga_size_flag 1
#### } elseif {$BOARD_NAME=="adrv9364z7020"} {
####    set ultra_scale_flag 0
####    set part_string xc7z020clg400-1
####    set fpga_size_flag 0
#### } else {
####    set ultra_scale_flag []
####    set part_string []
####    set fpga_size_flag []
####    puts "$BOARD_NAME is not valid!"
#### }
0 is not valid!
### set MODULE_NAME OPENOFDM_RX
### set  fd  [open  "./verilog/openofdm_rx_pre_def.v"  w]
### if {$NUM_CLK_PER_US == 100} {
###   puts $fd "`define CLK_SPEED_100M"
### } elseif {$NUM_CLK_PER_US == 200} {
###   puts $fd "`define CLK_SPEED_200M"
### } elseif {$NUM_CLK_PER_US == 240} {
###   puts $fd "`define CLK_SPEED_240M"
### } elseif {$NUM_CLK_PER_US == 400} {
###   puts $fd "`define CLK_SPEED_400M"
### } else {
###   throw {NUM_CLK_PER_US MUST BE 100/200/240/400!}
### }
invalid command name "throw"
    while executing
"throw {NUM_CLK_PER_US MUST BE 100/200/240/400!}"
    invoked from within
"if {$NUM_CLK_PER_US == 100} {
  puts $fd "`define CLK_SPEED_100M"
} elseif {$NUM_CLK_PER_US == 200} {
  puts $fd "`define CLK_SPEED_200M"
} elseif {$N..."
    (file "./openofdm_rx.tcl" line 51)
Vivado% exit

Hello,

I did all step successfully, but when I generated the bitstream, I have these problem? Do you konw what should I do?

Thanks in advance

Bohao

In file sync_long.v line 418-421, the original code is
stage_X0 <= cross_corr_buf[1];
stage_X1 <= cross_corr_buf[2];
stage_X2 <= cross_corr_buf[3];
stage_X3 <= cross_corr_buf[4];

I think the code should be fixed with:
stage_X0 <= cross_corr_buf[0];
stage_X1 <= cross_corr_buf[1];
stage_X2 <= cross_corr_buf[2];
stage_X3 <= cross_corr_buf[3];

I managed to synthesize everything with vivado 2022.1. The only thing that looks strange is, that the following inputs of tx_intf are unconnected:

dma_data
dma_valid

Is that correct or a problem with my vivado 2022.1?

Dear Xianjun,

I have a question about rssi calculation in module xpu. The average of IQ absolute value is used instead of IQ energy which usually denoted as the square of IQ. Is there any special assumption on this?

Thanks,
Lei

I think it should be possible to get openwifi running on plutosdr, if the sidechannel could be disabled with a parameter. I already found some places where ressource usage could be reduced, the iq-balance and dc offset correction in the AD936x hdl can be deactivated by parameters, they are not used anyway, because AD936x implements these features in hardware. There is also an additional 128 tap fir filter in the ad936x hdl code which is not used, that could also be eliminated.

Having some support for PlutoSDR would be very cool, because it is the cheapest AD936x hardware by far (250 USD).

Hi,
I would like to evaluate this project but since the target is the zc706 board with a zynq xc045 device a Vivado license is needed and it's not free.

I tried to modify the target to the ZC702 eval board with the same FPGA than the Zedboard the xc7z020clg484 device by simply repurpose the goal device in tcl project and IP cores but after compile the design you provide the implementation is not possible due not enough resources.

Here you have the utilization report from Vivado syntesys:

The resources exceed in SLUTs and DSPs. The first problem is about 13200 Slice LUTs that don't know how to reduce the design to achieve the goal since it's a big difference.

The DSPs maybe is easier to achieve, the 43 DSPs could be reduced by deleting the dds inside the ad9361(40 DSPs blocks) and re purpose other instance to use logic cells instead of DSPs.

I read in your road map this board will be compatible but seem a project redesign is needed unless i'm wrong in my test.

My desired goal would be the pluto board but I guess this will not be possible due the enormous lack of logic cells needed in this implementation.¿any approach to make it suitable for pluto board or zedboard?.

Hello Dr. Jiao! I am learning about your openwifi project. When I saw the csma module, I found that the backoff time directly began to decrease without waiting for DIFS. Is this in conflict with the violation?Thank you for taking time out of your busy schedule to check this message.

hello,
excuse me,I have generated abitstream in Vivado. How can I run your applications in the SDK?

looking forward your reply

Please is it possible to extend openwifi to support 802.11af on any FPGA SoC? If yes, how much effort will be required?

802.11af defines enhancements to the 802.11 WLAN physical layer (PHY) and medium access control (MAC) specifications to support operation in the TV white space (TVWS) spectrum in the VHF and UHF bands between 54 and 790 MHz.

Thanks

Compiled openwifi-hw, pulled the latest github code, and followed the steps strictly. In the last step of "Generate Bitstream", the system module could not be found. See the attached file.

First of all thank you for your help.
I couldn't find the system.v sub-module which is attached into dropbox link shown below.
https://www.dropbox.com/s/wmvgghgtb90bjm4/issuePic.png?dl=0

https://github.com/open-sdr/openwifi-hw/blob/master/boards/adrv9361z7035/src/system_wrapper.v
Have a great day.

Hello,

I wanted to understand the design (IP and the project hierarchy) so I just wanted to load the design in vivado. I am getting the following error on 'source ./openwifi.tcl'.

# set_property -name "legacy_ip_repo_paths" -value "" -objects $obj
ERROR: [Common 17-54] The object 'project' does not have a property 'legacy_ip_repo_paths'.

Can this be because of the Vivado version? I am using the 2018.2 instead of 2018.3. Any help or source on just loading the design specific to ZCU102 would be helpful.

Thanks

Hello,

I wanted to verify the direct TX1A to RX1A wireless link. I am sending a stream of repeated data on the 'dac_data' bus (modified the 'tx_intf' module and added the ILAs on 'dac_data' and 'adc_data' buses). The 'dac_data' and the 'adc_data' buses are 64-bits. On the transmit side, the 'dac_data' only sends data on the lower 32-bits while the upper 32-bits are always zeros (only antenna-0 is used). On the receiving side, all 64-bits 'adc_data' come in randomly. I just wanted to see the data LOOPEDBACK from the TX1A to RX1A wirelessly. Can you please give me some advise on how to achieve this? As I am not able to find the transmitted data on the receive side.

1. Our image is used directly or you build your own image?
   The FPGA was modified a little.

2. What is your own modification?
   Modified the 'tx_intf' to send a stream of repetitive data pattern on 'dac_data' bus.

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
   UBUNTU 14.04
   VIVADO 2018.3
   Latest GitHub commit: 868aad3

4. Board/hardware type
   'ADRV9361-Z7035 + ADRV1CRR-BOB'

5. WiFi channel number
   TX1A/RX1A

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"
   I tried this with your original image as well (after just adding the ILAs on 'dac_data' and 'adc_data' buses; no functional modifications). The entire 'openwifi' project was working. While the beacon pattern was continuously sent on the transmit side 'dac_data', I was not able to capture that pattern on the receive side 'adc_data' bus (tried to find one data at a time).

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

0. Could you send email to [email protected] to introduce your self?

1. Our image is used directly or you build your own image?

2. What is your own modification?

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision

4. Board/hardware type

5. WiFi channel number

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

0. Could you send email to [email protected] to introduce your self?

1. Our image is used directly or you build your own image?

2. What is your own modification?

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision

4. Board/hardware type

5. WiFi channel number

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

I get these errors when trying to simulate openofdm_rx with Vivado 2018.3:

INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/frank/Documents/my_openwifi/openwifi-hw/boards/zc706_fmcs2/openwifi_zc706_fmcs2/openwifi_zc706_fmcs2.tmp/openofdm_rx_v1_0_project/openofdm_rx_v1_0_project.sim/sim_1/behav/xsim'
xvlog --incr --relax -prj dot11_tb_vlog.prj
ERROR: [XSIM 43-4307] Invalid entry in the project file, expecting a file name but specified path '../../../../../../../../../ip_repo/common/openofdm_rx/src' represents a directory name.
ERROR: [XSIM 43-3217] dot11_tb_vlog.prj (line 3): Incorrect project file syntax. Correct syntax is one of: vhdl <worklib> <file>, verilog <worklib> <file> [<file> ...] [[-d <macro>] ...] [[-i <include>] ...], or NOSORT. Presence of NOSORT on a line of its own disables file order sorting.
xvhdl --incr --relax -prj dot11_tb_vhdl.prj

Any suggestion? Thanks

Hi,
Following Quick Start instructions I can see openwifi AP on my phone and get connected successfully. However, after updating latest FPGA bitestream following Update FPGA instructions. My board always get hanged.

I use

Ubuntu 18.04.5 LTS
Vivado 2018.3 without license
Analog Device ADRV9361-Z7035

I don't see any error message during BOOT.BIN generation. After I replace BOOT.BIN on SD card / power cycle and try to inite ~/openwifi/fosdem-11ag.sh

...
...
...

initiationsdr,sdr openwifi_dev_probe: test_mode 0
sdr,sdr openwifi_dev_probe: rfkill radio on
sdr,sdr openwifi_dev_probe: band_2GHz.n_channels 14 n_bitrates 12 band_5GHz.n_channels 11 n_bitrates 12
sdr,sdr openwifi_dev_probe: mac_addr 66:55:44:33:22:d5
ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
sdr,sdr openwifi_dev_probe: ieee80211_register_hw 0
ieee80211 phy0: hwaddr 6655443322d5, ZYNQ + ad9361
sdr,sdr openwifi_rfkill_init: wireless switch is on
sdr,sdr fpga-axi@0:sdr sdr0: renamed from wlan0
stop: Unknown instance:
isc-dhcp-server start/running, process 2263
Configuration file: hostapd-openwifi-11ag.conf
sdr0: interface state UNINITIALIZED->COUNTRY_UPDATE
Using interface sdr0 with hwaddr 66:55:44:33:22:d5 and ssid "openwifi"
NOT COMPLETE THE WHOLE PROCESS HANGED HERE

board get hanged every time without complete the whole initiation process. So I cannot see openwifi AP nor use it.

Would you please help to advised which part may I go wrong? Thank for your great help.

May I ask which licenses Vivado needs besides Xilinx Viterbi Decoder license, because the Bitstream and HDF files we often compile cannot be used, thank you

Dear Xianjun,

I have a question on the design of the retransmission in module "xpu" and "tx_intf”. We see the former retransmission can be stopped with another new transmission in queue 0, while other queues cannot be. What's the case for this? And why new transmission can go only when it's not in retransmission state for other queues (1,2,3) ??

Thanks.
Lei

Hello,

I am trying to simulate 2 projects separately, the 'openofdm_tx' and the 'openofdm_rx' modules in Vivado 2018.3. I wanted to run some tests for the legacy type packets. So I have a file that consists of a packet in the legacy format and I feed that to the 'openofdm_tx' project simulation. It captures the IQ data in: /openofdm_tx/openofdm_tx/openofdm_tx.sim/sim_1/behav/xsim/dot11_tx.txt
I then take this IQ file and apply as an input to the 'openofdm_rx' module.

***ISSUE: for small legacy type packet, the entire packet including the CRC on the receive side on signal 'byte_out' in 'dot11.v' matches ('fcs_ok' pulse can be seen coming out) but, if I modify the data in the packet, the data part on the RX side matches but the last 4 Bytes of CRC on the 'byte_out' signal does not match (causing 'fcs_ok' to not come out).

1. Our image is used directly or you build your own image?
   YES, your image is used directly.

2. What is your own modification?
   Only the memory input files for the simulation.

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
   UBUNTU 14.04
   VIVADO 2018.3
   Latest GitHub commit: 868aad3

4. Board/hardware type
   'ADRV9361-Z7035 + ADRV1CRR-BOB'

5. WiFi channel number
   TX1A/RX1A

6. Steps to reproduce the issue, and the related error message, screenshot, etc.

WORKING PART:

• In the 'openofdm_tx' project, copy the legacy packet (79 Bytes length) to the file 'tx_intf.mem' from:
  tx_legacy_pkt.txt

• Run the simulation, check the 4 Bytes of CRC generated: 32'h10F11AA1
  

• This will be transmitted out on the IQ Bus.

• Either copy the contents of the IQ Data or use this:
  dot11_tx_legacy_iq.txt

• Apply this file as an input to the 'openofdm_rx' project. On the 'byte_out' bus, we should be able to see the data coming byte-by-byte including the last 4 Bytes of the CRC. We can also see the 'fcs_ok' coming out.
  

NON-WORKING PART:

• In the 'openofdm_tx' project, copy the legacy packet (that is now modified, increased length to 304 Bytes randomly) to the file 'tx_intf.mem' from:
  tx_legacy_pkt_mod.txt

• Run the simulation, check the 4 Bytes of CRC generated: 32'hE14A2D84
  

• This will be transmitted out on the IQ Bus.

• Either copy the contents of the IQ Data or use this:
  dot11_tx_legacy_iq_mod.txt

• Apply this file as an input to the 'openofdm_rx' project. On the 'byte_out' bus, we should be able to see the data coming byte-by-byte, but, in this case, the last 4 Bytes of the CRC will not match. Causing the 'fcs_ok' signal to not come out.
  

Can you please help me understand why would this happen? What can be done to receive the correct data on the receive side in its entirety (including the CRC)?
NOTE: In some cases for simulation, there are times where the last 4 Bytes of the CRC plus some (last 1 to 4) Bytes of the data does not match.

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?

Hello, Dr. Jiao.
We are using your image.
My modification
I saw that the top file for side_ch had a predefined data bit width and thought I could modify it directly. So, I tried modifying the side_ch IP Core of the FPGA , I want to use it to get more information at the same time, because I want to add some functionality, I tried to change the bit width of the data from side_ch to PS using DMA directly from 64bit to 128bit, and the width of the device tree to 128bit, but when using Linux script:./side_ch_ctl g.The side_info_count does not increase, which means no data send to PS.

Our Board/hardware type:
Based on fcms2+zedboard.

My debug efforts:
After a lot fruitless attempts, I looked at some of the signals using ILA and found that the AXI, which might be used to control the SIDE_CH cycle for data acquisition, might not be working properly.

The above is the online Debug diagram of my modified FPGA project.

The above is yours.
The key is that the signal line slv_reg_wren, which should appear periodically.After the modification, it only becomes high the first time I execute insmod side_ch.ko and./side_ch_ctrl g.
I guess:Perhaps AXI is not working properly because DMA is passing 128 bits at a time but only 64bit is coming out?
Could you give me some suggestions about changing the data bit width?

Hi
I want to know that what is data format of IQ in 16 bit in receive side?
In demodulater.v why scaling is taken 1024 though input is in 16 bit?
Regards
J S Hyanki

Hello,
I've tried to build adrv9361z7035 FPGA bit file from scretch but fail. Fail at prepare_adi_board_ip.sh process. I got the error message as below. Could you help to advise what may go wrong? BTW, I've tried all the board supported. Only zed_fmcs2 , adrv9364z7020 , zc702_fmcs could successfully complete the whole script process.

vivado.log

-----------------------------------------------------------
# Vivado v2018.3 (64-bit)
# SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
# IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
# Start of session at: Fri Apr 23 10:35:46 2021
# Process ID: 11123
# Current directory: /home/xw/trial/openwifi-hw/adi-hdl/projects/adrv9361z7035/ccbob_lvds
# Command line: vivado -mode batch -source system_project.tcl
# Log file: /home/xw/trial/openwifi-hw/adi-hdl/projects/adrv9361z7035/ccbob_lvds/vivado.log
# Journal file: /home/xw/trial/openwifi-hw/adi-hdl/projects/adrv9361z7035/ccbob_lvds/vivado.jou
#-----------------------------------------------------------
source system_project.tcl
# source ../../scripts/adi_env.tcl
....
..
.
# set p_device "xc7z035ifbg676-2L"
# adi_project adrv9361z7035_ccbob_lvds
WARNING: [Device 21-436] No parts matched 'xc7z035ifbg676-2L'
ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Fri Apr 23 10:35:52 2021...

@black-pigeon

I am trying to take e310v2 changes from your antsdr branch. Since in our side we have already moved fpga img files to openwifi-hw-img repository and we do not have sdk directory in openwifi-hw/boards/antsdr_e200 anymore, so would you please remove the sdk directory in openwifi-hw/boards/antsdr_e200 after this commit:
MicroPhase@c66c001

Then I can check whether this will bring us a cleaner merge via the pull request that I already created.

Following the guide in readme.md to generate bitstream for zc702_fmcs2 board with code version 8cdaf54. No any code change. It fails.
Host OS: Ubuntu LTS 22.04 with Vivado Simulator 2018.3

Below is warning and error report from elaborate.log:
WARNING: [VRFC 10-3715] size mismatch in mixed language port association, vhdl port 'm_axis_data_tdata' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/ofdm_decoder.v:109]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'dc_running_sum_th' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/dot11_tb.v:444]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/moving_avg.v:36]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'web' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/moving_avg.v:43]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/delay_sample.v:29]
WARNING: [VRFC 10-3091] actual bit length 3 differs from formal bit length 2 for port 'state' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/dot11.v:364]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/sync_long.v:166]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'phase' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/sync_long.v:186]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/equalizer.v:205]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'enb' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/equalizer.v:211]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/equalizer.v:247]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'enb' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/equalizer.v:253]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/deinterleave.v:135]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'enb' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/deinterleave.v:141]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'web' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/deinterleave.v:142]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 16 for port 'dib' [/home/user/workspace/Position/fpga/openwifi-hw/ip/openofdm_rx/verilog/deinterleave.v:144]
Completed static elaboration
Time Resolution for simulation is 1ps
Compiling package std.standard
...........
Compiling module xil_defaultlib.glbl
ERROR: [XSIM 43-3409] Failed to compile generated C file xsim.dir/dot11_tb_behav/obj/xsim_11.c.
ERROR: [XSIM 43-3915] Encountered a fatal error. Cannot continue. Exiting...

Hi
i have doubt in soft decoding applied in FEC.
output of de-modulator in 64QAM case, output bit width is six for hard decoding as well as soft bits.
How is it possible, I guess no of soft bits will be more than no of hard bits?
Why it is same here?
Regards
Hyanki

Hello, I want to try to port the project from zc706 - ad9361 to zc706 - adrv9375, can you give advice on how to do it correctly and what difficulties it can be, as I understand one of the problems is setting up ad9375 itself, as I see the source hdl for ad9375 is very different, is jesd204b used?
vivado 2018.3, zc706-adrv9375, adi linux 2019R1

0. Hello, I have 2 separate sets of 'ADRV9361-Z7035 + ADRV1CRR-BOB' boards that has working openwifi. I wanted to use one of the boards as it is with running openwifi (host board) and the other board as client (connecting to the 'openwifi' network by the host board). Can you please give me some info on how this can be achieved?

1. Our image is used directly or you build your own image?
   yes

2. What is your own modification?
   none so far

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
   UBUNTU 14.04
   VIVADO 2018.3
   Latest GitHub commit: 868aad3

4. Board/hardware type
   two qty. 'ADRV9361-Z7035 + ADRV1CRR-BOB'

5. WiFi channel number
   TX1A/RX1A

6. Steps to reproduce the issue, and the related error message, screenshot, etc

7. Describe your debug efforts by Linux native tools, such as tcpdump and "cat /proc/interrupts"
   From the client board, I tried to look for the 'openwifi' network that has different MAC and IP ADDR for SDR0 port but are in the same subnet, still not able to connect if both the boards are ON and close to each other. At times, it will affect other WiFi connected devices (like laptop).

8. Describe your debug efforts by: https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Debug-methods

9. Any other thing we need to know for helping you better?
   Need the advice on how this connection can be achieved?

Hello ,
is there a way to make my openwifi HDL project using vivado version 2021 ML edition ?

Hello,

0. I am working with the boards 'ADRV9361-Z7035 + ADRV1CRR-BOB' and was successfully able to create 'openwifi' SSID, connect to it and load the local host page through phone. I am now trying to add some ILAs to the HW-Design inside the openwifi-ip based on the module inputs 'adc_clk' and 'm_axi_mm2s_aclk' clocks.

1. Our image is used directly or you build your own image?
   Yes, your image is used directly.

2. What is your own modification?
   Added some ILAs inside the openwifi-ip. If I just use the 'adc_clk' and 'm_axi_mm2s_aclk' clocks for the ILAs, after running the project on board and connecting the board to the system via JTAG, the ILAs does not load directly on the Vivado Hardware Manager. If I try to program the board from Vivado, then I can see the ILAs but I am getting errors in running the openwifi_ap '~/openwifi/fosdem-11ag.sh' on board.I believe the issue here is that I need some free-running clocks for ILAs. Can I get some help on this? Also, can you please confirm some things as my understanding is that 'adc_clk' is 100MHz and 'm_axi_mm2s_aclk' is 200MHz for the 'openwifi_ip'?

3. Versions: OS, Vivado, openwifi/openwifi-hw repo branch and commit revision
   UBUNTU 14.04
   VIVADO 2018.3
   Latest GitHub commit: 868aad3

4. Board/hardware type
   'ADRV9361-Z7035 + ADRV1CRR-BOB'

5. WiFi channel number:
   TX1A/RX1A

6. Steps to reproduce the issue, and the related error message, screenshot, etc
   Add an ILA inside the openwifi-ip, with 3 inputs: 'dac_ready', 'dac_valid' & 'dac_data' and clock input 'adc_clk'. Mark all 3 inputs as 'debug'. Synthesize the design and follow the same steps for the 'ADRV9361-Z7035 + ADRV1CRR-BOB/FMC' project. Connect the board to the system with Vivado via JTAG cable, open Vivado Hardware Manager and 'auto-connect' to the board. Once the board is loaded, ideally, it should also load ILAs on the Vivado Hardware Manager. But, I can't see those so I think, I need free-running clocks coming from the board that is same as the 'adc_clk' frequency.

Thanks

in ad9361 manual the register of tx
Lo control is 0x051,but in spi.v the register data is
"define SPI_HIGH 24'hC22001", reverse of spi data is 0x800443, the address is 0x004,why not 0x051？

Do you think it is a good idea to combine your project with the 802.1AS protocol?Will this workload be heavy?

hello sir,
thank you for your amazing work.I would like to ask you some tips about the module “sync_short”. There is a output named “phase_offset”,Is this the frequency offset you calculated using a short training sequence(coarse estimation)? I read the comment and found that it seems to be approximated as an integer, what is its range? If I can understand this information, it will definitely be very helpful for my learning. Looking forward to your reply!