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Example projects/code for the OrangeCrab

License: MIT License

Makefile 10.64% C 40.05% Assembly 1.95% Verilog 7.78% Python 39.57%

orangecrab-examples's Introduction

OrangeCrab example projects

This repository contains example code to be run on the OrangeCrab.

RISCV examples

These examples make use of the Vexriscv CPU created inside the FPGA by the bootloader. The RISCV firmware is copied across into the FLASH by the bootloader. If the bootloader determines that it has not loaded new gateware, then the CPU will simply adjust it's program counter to start executing the newly loaded programs.

riscv.blink - The most basic example. Blink a LED with RISCV firmware
riscv.button - Read button input and toggle LED colour

Verilog examples

These examples use Yosys + NextPnR, to synthesis (or compile) verilog into a bitstream. A nice term for this is gateware. Since it is analogous to firmware, but describes how the FPGA needs to be configured.

This gateware can be loaded onto the OrangeCrab using its DFU bootloader.

verilog.blink - The most basic verilog example. Blink a LED with gateware

Amaranth examples

These example use Amaranth + Yosys, to synthesis (or compile) the Python based hardware description language into gateware. Amaranth will by default then automatically load the gateware onto the OrangeCrab using its DFU bootloader.

Miscellaneous

If you are using a recent version of Ubuntu, you will not be able to access the dfu bootloader using normal permissions. You can use the included udev rule 50-orangecrab.rules to grant access to the orangecrab device to the plugdev group.

To install, type this command in a terminal:

$ sudo cp 50-orangecrab.rules /etc/udev/rules.d/50-orangecrab.rules

After this file is installed, physically unplug and reconnect the orangecrab device.

RISC-V Cross Compiler Toolchain

To cross-compile for the bootloader's VexRiscv rv32i processor, you need a RISC-V compiler toolchain that includes support libraries for rv32i. Debian and Ubuntu currently have riscv64-unknown-elf compilers that will cross-compile for rv32i. But, to use those, you would need to build your own support libraries (libc, etc). For a ready-to-use option, you can download an embedded RISC-V toolchain from Embecosm's Tool Chain Downloads page.

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orangecrab-examples's Issues

Pinout does not show SD pins.

The pinout sheet shown here:
https://gregdavill.github.io/OrangeCrab/r0.2/docs/pinout/

Does not show pins required for accessing the SD card.

hw.r0.2: Missing pins in pin constraint file

From 1BitSquared.orangecrab discord:

There are some pins marked SCL and SDA on the orangecrab but the constraint file I downloaded from https://github.com/orangecrab-fpga/orangecrab-examples/tree/main/verilog doesn't seem to enable any way to access them. Is there a better constraint file with access to more pins? (also MOSI/MISO, gpio a4/a5)

LiteX SoC example fails synthesis on recent Yosys

When building the litex CircuitPython SoC example with Yosys eef0ec6a, the following error is encountered:

4.39. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
ERROR: Conflicting init values for signal 1'0 (\soc_basesoc_interface_adr [5] = 1'x != 1'0)

Not sure if this is a regression or there's an actual driver conflict. I'll try to look into it.

Add full PCF for examples

The current verilog examples only contain a partial pcf,.
It will be useful to have a full pcf created as a reference for peoples projects.

The litex example does not work for me at HEAD

Hi Greg,
I do not have much experience with verilog and migen/litex, so I build and tested all examples. The examples work except litex. The last working commit for litex is a750e68. At HEAD usb does not enumerate.

My build environment is Arch Linux, riscv gcc from SiFive and fpga-toolchain nightly-20201011 from open-tool-forge.

Due to my lack of experience I do not know how to proceed to fix this issue. Please let me know if you need more information.

Michael

[Clarification] USB questions

Hey,
I have some questions regarding the USB, specially because I saw the orange crab bootloader SoC (https://github.com/gregdavill/foboot/tree/OrangeCrab) and there the USB is added "differently"
In these lines I see that you attach the USB into a seperate CSR Bus.

Why is it necessary? In the bootloader this isn't the case, and is the fact that the USB is attached to a sperate CSR BUS why a new csr header file (usb_csr.h) is created?
Why does the USB need to be in a CSR bus that's decoupled from our CPU clock? Taking into consideration that in the bootloader SoC this does not happen

In this line the USB interrupt is added (I think). In the bootloader, there is not an explicit USB interrupt addition like this, because I think this is done in the platform.finalize(). However, in the CircuitPython example, there is no platform.finalize().

Why did you add this line and why isn't the platform.finalize() called in this example when the bootloader does?

PCF files do not match the actual pinout for GPIOs

It appears that the GPIO pins in the pcf file here: https://github.com/gregdavill/OrangeCrab-examples/blob/main/verilog/orangecrab_r0.2.pcf are not correct.

They do not match the pinout here: https://gregdavill.github.io/OrangeCrab/r0.2/docs/pinout/ and at least from my quick look at the schematic, the picture is the correct reference.

85F compatiblity

Now that we OrangeCrabs available with 85F parts we should add some words to the docs about targeting either the 25F or 85F.

pwm_rainbow make fails

Hi,
Sorry if I am putting it here on github.
I have just got started with FPGAs and I got this kit. now everything works fine I am able to build blink and test it on device but when I try to make the pwm_rainbow example the build fails when I run 'make'

-- Executing script file pwm_rainbow.ys' --
ERROR: Can't open script file pwm_rainbow.ys' for reading: No such file or directory

JSON backend fails on verilog blink

With today's tip of main branch and today's pack of the OSS CAD Suite, the simplest example -- verilog/blink -- fails to build for me, yielding the following error:

~/orangecrab-examples/verilog/blink $ source ~/oss-cad-suite/environment
(OSS CAD Suite) ~/orangecrab-examples/verilog/blink $ make
yosys -p "synth_ecp5 -json blink.json" blink.v
...
...
2.49. Printing statistics.

=== top ===

   Number of wires:                 10
   Number of wire bits:            119
   Number of public wires:           5
   Number of public wire bits:      31
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              2
   Number of cells:                  3
     $add                            1
     $not                            2

2.50. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

2.51. Executing JSON backend.
ERROR: Module top contains processes, which are not supported by JSON backend (run `proc` first).
make: *** [Makefile:32: blink.json] Error 1
rm blink.json

Am I missing something obvious?

Sending data to/from the FPGA with a ValentyUSB core

I am trying to access the W25Q128JVP flash on this board (r0.2.1) using a QSPI flash controller, but I want to confirm if there might be an easier way to do this. I want to send data to and from the board using the DFU interface, which lets me read and write to the flash. Is there an example of a QSPI flash controller that interfaces with the flash on this board, or will some existing controller such as this work? Or is there a way to interface with the DFU bootloader from within the FPGA fabric?

I don't think it's possible to write to arbitrary memory locations on the flash via DFU since this device doesn't implement DfuSe. The question I have now becomes: What is a good solution for sending data to/from the board from a host PC? There is not an FTDI chip on this board so the only solution I know of is to use a valentyusb core which I think exposes a uart interface to the FPGA. But I am not sure how to use this core without a SoC, all the examples I see demonstrate it's usage with liteX and a SoC.

device

Is possible add power, screen and input keyboard?
similar https://hackaday.io/project/9692-ello-2m but with small gpio.
fpga is no problem, but problem is with power (for example 2 AA is for week working linux on psion 5)
screen, keyboard enclosure and meybe internet (ethernet, irda, rs, usb etc)
Why not all packing into keyboard similar zx88 or https://luigigardening.com/lisperati1000-raspberry-pi-based-ultra-compact-device-for-programming/

RISC-V Blink and Button examples fail to build

When running make all for the blink or button examples in the riscv folder, the command riscv64-unknown-elf-gcc comes up as unknown. Full error below:

$ make all
riscv64-unknown-elf-gcc  -march=rv32i -mabi=ilp32 -Wl,-Bstatic,-T,sections.ld,--strip-debug -ffreestanding -nostdlib -I. -o blink_fw                                                                                                                                                                                         .elf start.s main.c
make: riscv64-unknown-elf-gcc: Command not found
make: *** [Makefile:12: blink_fw.elf] Error 127

$PATH is set correctly and is being built on Ubuntu linux 64-bit. The verilog examples compile fine.

litex example cannot find Yosys or nextpnr-ecp5 programs

Greg,

I am trying to build the SoC for the orange crab but have had no luck so far. Here is the output when I try to build it:
~/FPGA_Dev/OrangeCrab-examples/litex$ python3 SoC-CircuitPython.py
lxbuildenv: v2020.6.1.1 (run SoC-CircuitPython.py --lx-help for help)
lxbuildenv: nextpnr-ecp5: nextpnr-ecp5 not found in your PATH -- None
lxbuildenv: yosys: yosys not found in your PATH -- None
lxbuildenv: To ignore dependencies, re-run with "--lx-ignore-deps"
2 missing dependencies were found

This is strange to me as these are in the PATH and I can verify by running the following just as the tutorial says:
~/FPGA_Dev/OrangeCrab-examples/litex$ yosys -V
Yosys 0.9+3477 (open-tool-forge build) (git sha1 3cb3978f, gcc 9.3.0-10ubuntu2 -Os)
~/FPGA_Dev/OrangeCrab-examples/litex$ nextpnr-ecp5 -V
nextpnr-ecp5 -- Next Generation Place and Route (Version nightly-20200801)

Here is the build with the --lx-print-env argument:
~/FPGA_Dev/OrangeCrab-examples/litex$ python3 SoC-CircuitPython.py --lx-print-env
lxbuildenv: v2020.6.1.1 (run SoC-CircuitPython.py --lx-help for help)
PYTHONPATH=/home/TH/FPGA_Dev/OrangeCrab-examples/litex/deps/litex-boards:/home/TH/FPGA_Dev/OrangeCrab-examples/litex/deps/litedram:/home/TH/FPGA_Dev/OrangeCrab-examples/litex/deps/valentyusb:/home/TH/FPGA_Dev/OrangeCrab-examples/litex/deps/pythondata-cpu-vexriscv:/home/TH/FPGA_Dev/OrangeCrab-examples/litex/deps/migen:/home/haines/FPGA_Dev/OrangeCrab-examples/litex/deps/litex
PYTHONHASHSEED=1
PYTHON=/usr/bin/python3
LXBUILDENV_REEXEC=1

Thanks for your help!

Analog examples

Provide an example using the analog pins.

Orange Crab r0.2 2019-12-08 won't enter bootloader mode.

I've been searching the internet to find a more appropriate place to report this, but I think this is probably the best place I've found, so opening an issue.

Just received my board from GroupGet and I can't enter DFU mode. I've confirmed my cabling is correct, I've tested the button with a multi-meter and it is working correctly.

When I hold down btn0 while plugging in the device I receive a solid green light and a solid white light, no different than when I plug in the device without holding the button down. I've confirmed my USB cables are data cables and can be handle serial communications with multiple micropython devices.

I am trying to figure out how to flash my own bootloader onto it, now, but the documentation outside of dfu-util use is sparse. All official documentation says to enter bootloader mode in this manner. I've watched video of people booting into bootloader mode and I'm certain I'm doing it correctly.

Am I missing something?

LED constraints

Hi Greg,

in my tests, it isn't really possible to use green & blue LEDs.
They are already being used to indicate the state the board is in.
ie steady Cyan indicates download complete.

Any attempt to set green or blue, to 1'b1 for instance, interferes and corrupts process.

Please could you investigate further?

iirc in my tests even your led projects as published do not operate as expected.

A few more projects would be great, perhaps some analog?
In other respects the board functions well, thanks!
xx

Running python3 SoC-CircuitPython.py fails

When I run python3 SoC-CircuitPython.py I get this error:

jamesmeech@Jamess-MacBook-Pro-10 litex % python3 SoC-CircuitPython.py           
lxbuildenv: v2020.6.1.1 (run SoC-CircuitPython.py --lx-help for help)
Traceback (most recent call last):
  File "/Users/jamesmeech/Desktop/Casino/orangecrab-examples/litex/SoC-CircuitPython.py", line 342, in <module>
    main()
  File "/Users/jamesmeech/Desktop/Casino/orangecrab-examples/litex/SoC-CircuitPython.py", line 306, in main
    soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)),**argdict(args))
                                                                                         ^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/orangecrab-examples/litex/SoC-CircuitPython.py", line 334, in argdict
    r = soc_sdram_argdict(args)
        ^^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/orangecrab-examples/litex/deps/litex/litex/soc/integration/soc_sdram.py", line 69, in soc_sdram_argdict
    r = soc_core_argdict(args)
        ^^^^^^^^^^^^^^^^^^^^^^
  File "/Users/jamesmeech/Desktop/Casino/orangecrab-examples/litex/deps/litex/litex/soc/integration/soc_core.py", line 320, in soc_core_argdict
    for a in inspect.getargspec(SoCCore.__init__).args:
             ^^^^^^^^^^^^^^^^^^
AttributeError: module 'inspect' has no attribute 'getargspec'. Did you mean: 'getargs'?

I assume that this means I should be using an earlier version of python. Which version should I be using?

Building the LiteX / CircuitPython example fails with recent toolchains

The most recent toolchains enforce stricter checks on passing compiler flags to the linker (see, e.g., apache/nuttx#3826 ). This results in the build failing as follows:

riscv32-unknown-elf-ld: Error: unable to disambiguate: -nodefaultlibs (did you mean --nodefaultlibs ?)
make: *** [bios.elf] Error 1
Traceback (most recent call last):
  File "/Users/ciro/OrangeCrab/orangecrab-examples/litex/SoC-CircuitPython.py", line 342, in <module>
    main()
  File "/Users/ciro/OrangeCrab/orangecrab-examples/litex/SoC-CircuitPython.py", line 318, in main
    vns = builder.build(**builder_kargs)
  File "/Users/ciro/OrangeCrab/orangecrab-examples/litex/deps/litex/litex/soc/integration/builder.py", line 207, in build
    self._generate_rom_software(not self.soc.integrated_rom_initialized)
  File "/Users/ciro/OrangeCrab/orangecrab-examples/litex/deps/litex/litex/soc/integration/builder.py", line 187, in _generate_rom_software
    subprocess.check_call(["make", "-C", dst_dir, "-f", makefile])
  File "/Users/ciro/miniforge3/lib/python3.9/subprocess.py", line 373, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['make', '-C', '/Users/ciro/OrangeCrab/orangecrab-examples/litex/build/orangecrab/software/bios', '-f', '/Users/ciro/OrangeCrab/orangecrab-examples/litex/deps/litex/litex/soc/software/bios/Makefile']' returned non-zero exit status 2.

Toolchain info:

litex % riscv32-unknown-elf-gcc -v
Using built-in specs.
COLLECT_GCC=riscv32-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/opt/riscv/libexec/gcc/riscv32-unknown-elf/11.1.0/lto-wrapper
Target: riscv32-unknown-elf
Configured with: /Volumes/RISCV/riscv-gnu-toolchain/riscv-gcc/configure --target=riscv32-unknown-elf --prefix=/opt/riscv --disable-shared --disable-threads --enable-languages=c,c++ --with-pkgversion=g --with-system-zlib --enable-tls --with-newlib --with-sysroot=/opt/riscv/riscv32-unknown-elf --with-native-system-header-dir=/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --disable-tm-clone-registry --src=.././riscv-gcc --disable-multilib --with-abi=ilp32d --with-arch=rv32imfdc --with-tune=rocket --with-isa-spec=2.2 'CFLAGS_FOR_TARGET=-Os   -mcmodel=medlow' 'CXXFLAGS_FOR_TARGET=-Os   -mcmodel=medlow'
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 11.1.0 (g)

RISC-V examples: Add SoC register map / explaination.

Received an inquiry over email.

Hi, is there any documentation or API reference guide for programming the OrangeCrab and targeting the RISC-V ISA? I noticed that in https://github.com/gregdavill/OrangeCrab-examples/blob/main/riscv/button/main.c there were calls to functions such as timer0_en_write() and rgb__r_write(), so is there any central doc that has peripheral documentation? Thanks.

When loading RISCV code directly as the examples illustrate, what is actually running this code is the SoC loaded into the FPGA by the bootloader. This processor is a bit limited, it currently only runs at 12MHz and does not contain a DDR3 memory controller.
This is the project for the bootloader: https://github.com/gregdavill/foboot/tree/OrangeCrab

Right now we don't have a referenced document about register maps for that SoC. We should set one up.

LiteX has a mechanism to generate very nice HTML documentation for register maps, but we're currently not storing this anywhere.
https://github.com/gregdavill/foboot/blob/OrangeCrab/hw/foboot-bitstream.py#L335

Linux on RiscV

Please show simple example linux on risc-v

OrangeCrab r0.2.1 no longer enumerating through dfu-util

i have a newly-purchased orangecrab board that is no longer enumerating through dfu-util --list.... worse, the green power led no longer illuminates when i power the board through usb; and the continually changing rgb led is basically frozen....

wanting to program the board through jtag, i connected an adafruit ft232h board to the orange crab as follows:

i also chose to power the orange crab using 5V taken from the adafruit board....

when i would run ecpprog -t, however, all of the ID bytes were 0x0; further attempts to read flash also returned 0x0....

assuming i haven't fried my orangecrab, is there any path to return the board to its original (working) state????

Verilog Example Build Error

I followed the getting started guide exactly as instructed here: https://gregdavill.github.io/OrangeCrab/r0.2/docs/getting-started/ and while building with make encountered this error:

Generating RTLIL representation for module `\LUT4'.
ERROR: Assert `(unsigned)*c > (unsigned)' '' failed in ./kernel/rtlil.h:168.
make: *** [Makefile:13: blink.json] Error 1

I was attempting to build the verilog blink program for the r0.2 on x86_64 Windows 10. The toolchain was downloaded and the bin directory was added to the system PATH and works fine.
Full output here:

> make
yosys -p "synth_ecp5 -json blink.json" blink.v

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Wolf <[email protected]>          |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+2406 (open-tool-forge build) (git sha1 eef0ec6a, x86_64-w64-mingw32-g++ 10.1.0 -Os)


-- Parsing `blink.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend: blink.v
Parsing Verilog input from `blink.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

-- Running command `synth_ecp5 -json blink.json' --

2. Executing SYNTH_ECP5 pass.

2.1. Executing Verilog-2005 frontend: D:\Hackster Show Projects\Spotlight\Orange Crab\Code\fpga-toolchain-windows_amd64-nightly-20200712\fpga-toolchain\bin\../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `D:\Hackster Show Projects\Spotlight\Orange Crab\Code\fpga-toolchain-windows_amd64-nightly-20200712\fpga-toolchain\bin\../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
ERROR: Assert `(unsigned)*c > (unsigned)' '' failed in ./kernel/rtlil.h:168.
make: *** [Makefile:13: blink.json] Error 1

CircuitPython isn't exporting board?

I'm terribly sorry for being a CircuitPython n00b and I acknowledge that this CircuitPython instance appears to be a specialization of the Fomu CircuitPython which is a version of the Litex CircuitPython, but I'll start nearest to what I tested.

I can launch CircuitPython just fine, but the pins in ports/litex/boards/orangecrab/pins.c (only RGB? No button? No GPIOs?) should show up in module board IIUC, but it isn't exported?

Adafruit CircuitPython 5.0.0-alpha.0-2979-gd7574482d on 2021-08-25; OrangeCrab with VexRiscv
>>> 
>>> import board
Traceback (most recent call last):
  File "<stdin>", line 1, in <module>
ImportError: no module named 'board'
>>>

Am I missing something obvious?

Unable to enter DFU mode using a GPIO pin

Hello, I'm fairly new to FPGA development and I apologise if this is an obvious mistake.

I'm trying to get the Orangecrab (85F) to enter DFU mode when I press an external momentary switch that I have wired up on a breadboard. I have connected 3V3 from the Orangecrab through a switch and into GND via a 10k ohm resistor. I then adapted the blink_reset.v example to read input gpio_10 and set reset_sr low when the button is pressed.

When I press the switch the orange crab resets. When I press and hold the switch, the onboard RGB LEDs are high (blue/green are maybe 50% and red is maybe 25%). In either case, the device doesn't enter DFU mode. The LEDs stop flashing during this time which leads me to think the device keeps resetting? I've tried debouncing the switch but that didn't seem to work. I'd appreciate any help you can provide. Thank you.

// blink_reset.v - modified
module top (
    input clk48,

    output rgb_led0_r,
    output rgb_led0_g,
    output rgb_led0_b,

    output rst_n,
    input usr_btn,
    input gpio_10
);
    // Create a 27 bit register
    reg [26:0] counter = 0;

    // Every positive edge increment register by 1
    always @(posedge clk48) begin
        counter <= counter + 1;
    end

    // Output inverted values of counter onto LEDs
    assign rgb_led0_r = ~counter[24];
    assign rgb_led0_g = ~counter[25];
    assign rgb_led0_b = 1;

    // Reset logic on button press.
    // this will enter the bootloader
    reg reset_sr = 1'b1;
    always @(posedge clk48) begin
        reset_sr <= {~gpio_10};
    end
    assign rst_n = reset_sr;


endmodule