MIPS Processor(Harvard Architecture)

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.

In addition to an assembler to decode assembly code files to fill the instruction memory with the right data

⚙ ISA Specifications

Registers:
- R[0:7]: Eight 16-bit general purpose registers
- PC: 32-bit program counter register
- SP: 32-bit Stack Pointer register
- EPC: 32-bit Exception Program Counter register
- CCR: Condition Code Register
  - Z: zero flag
  - N: negative flag
  - C: carry flag
Ports:
- IN port: 16-bit data input port
- OUT port: 16-bit data output port

📋 Instruction Set

One Operand Instructions	Two Operand Instructions	Memory Instructions	Branch Instructions
NOP	MOV Rsrc, Rdst	PUSH Rsrc	JZ Rdst
HLT	ADD Rdst, Rsrc1, Rsrc2	POP Rdst	JC Rdst
SETC	SUB Rdst, Rsrc1, Rsrc2	LDM Rdst, Imm	JN Rdst
NOT Rdst	AND Rdst, Rsrc1, Rsrc2	LDD Rdst, offset(Rsrc)	JMP Rdst
INC Rdst	IADD Rdst, Rsrc1, Imm	STD Rsrc1, offset(Rsrc2)	CALL Rdst
OUT Rsrc	-	-	RET (for call)
IN Rdst	-	-	INT index
-	-	-	RTI (for interrupt)

Instruction

5-bit Opcode	3-bit src1 register address	3-bit src2 register address	3-bit dst register address	1-bit for hlt	1-bit (not yet used)	16-bit offset

🎗 Features

reset signal
Successful hazards detection and handling (using full forwarding)
Successful Interrupts calling
Successful Exceptions handling
- Exception 1: empty stack
- Exception 2: invalid addess

🔄 Pipeline Stages

1️⃣ Fetch Stage

2️⃣ Decode Stage
2️⃣ Execute Stage

Run

cd to where you want to clone the repo
run git clone https://github.com/Passant-Abdelgalil/MIPS-Processor-Harvard-Architecture.git
run cd MIPS-Processor-Harvard-Architecture
to run the assembler with your file, run python ./Assembler/assembler.py code_file="./Test_Cases/branch_code.asm"
Create a project in modelsim, Tutorial
To run Do files, in the transcript window run do ./Do_files/<do file name you want to run>
Or start your own simulation :)

Contributors

_{Mohamed Akram}

_{Passant Abdelgalil}

_{Mariam Ashraf}

_{Esraa Gamal}

passant-abdelgalil / mips-processor-harvard-architecture Goto Github PK

mips-processor-harvard-architecture's Introduction

MIPS Processor(Harvard Architecture)

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.

In addition to an assembler to decode assembly code files to fill the instruction memory with the right data

⚙ ISA Specifications

📋 Instruction Set

Instruction

🎗 Features

🔄 Pipeline Stages

1️⃣ Fetch Stage

2️⃣ Decode Stage

2️⃣ Execute Stage

Run

Contributors

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passant-abdelgalil / mips-processor-harvard-architecture Goto Github PK

mips-processor-harvard-architecture's Introduction

MIPS Processor(Harvard Architecture)

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture. In addition to an assembler to decode assembly code files to fill the instruction memory with the right data

⚙ ISA Specifications

📋 Instruction Set

Instruction

🎗 Features

🔄 Pipeline Stages

1️⃣ Fetch Stage

2️⃣ Decode Stage

2️⃣ Execute Stage

Run

Contributors

Recommend Projects

Recommend Topics

Recommend Org

A Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.

In addition to an assembler to decode assembly code files to fill the instruction memory with the right data