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bme351's Issues

optimization

course chap. 6

possible optimization techniques

Replication and Sharing

  • mux pushing
  • common subexpression elimination
  • computation replication
  • input trimming

no

max1
    in1  : 7 downto 0
    in2  : 7 downto 0
    out  : 7 downto 0

reg1
    out : 7 downto 0

reg2
    out : 8 downto 0
add1
    in1 : 7 downto 0
    in2 : 7 downto 0
    out : 8 downto 0

add2
    in1 : r1 -> max1 -> 7 downto 0
    in2 : r2 -> add1 -> 8 downto 0
    out : 9 downto 0

add3 (cycle 2)
    in1 : r2 -> add1 -> 8 downto 0
    in2 : r4 -> r2   -> 8 downto 0
    out : 9 downto 0

add3 (cycle 3)
    in1 : r2 -> add1 -> 8 downto 0
    in2 : (add3-cycle2) -> 9 downto 0
    out : 10 downto 0

add3 (cycle 4)
    in1 : 8 downto 0
    in2 : 10 downto 0
    out : 11 downto 0

max2
    in1 : r3 -> 9 downto 0
    in2 : r3 -> 9 downto 0
    out : 9 downto 0

r5 (after left shifting 3 bits)
    out : 12 downto 0


r6 (S4-1)
    in: add2 -> 11 downto 0

r7 (S4-1)
    in: add3 -> 11 downto 0

add4
    in1 : r7    -> 11 downto 0
    in2 : r7<<1 -> 12 downto 0
    out : 13 downto 0

r6
    in  : add4 -> 13 downto 0
    
sub1
    in1 : (signed) r5 -> 12 downto 0
    in2 : (signed) r6 -> 13 downto 0
    out : (signed) 13 downto 0

1st Feedback from Eric

Stuff to fix

  • "Blue area is large, means you are having edges that shouldn't"
    • see picture below (generated by diff_ted_to_bmp)

res1_sim_diff

Stuff to improve

  • "Bit width is way too large for the last stage." (He meant those 16 downto 0 ones
    • see issue #3

Eric Commits

Another comments Eric made were that

  • we're not having any skew (see the blue image above), which is a good thing
  • he has never use resize() before, and suggest we use leading 0 and & to do resizing.
  • don't worry about direction right now, try to do the computation manually for the first few rows to see what your problem(s) is

@ali-abdullah @mosobase @sepehrafla

Draw new DFD using draw.io

  • Draw a new DFD based on following hand-written DFD
  • Requirements:
    • same quality as our dfd-prelim (dfd-name.pdf under kirsch_proj/)
    • label stages with distinct color
    • label each operator/component with its name (eg max1, r1)
    • clear data flow (eg arrow, lining)
    • Overlapping stages must have same alignment to clearly show clock cycles
    • same box size for each operator (max, add, sub, shift comp)
      new_dfd

fix new clock cycle

we introduced a new clock cycle to compensate the final output in #7 ... need to fix it

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