richjyoung / vscode-modern-vhdl Goto Github PK

Might help #13, worth having anyway.

Hi Rich, congrats for the hard work, I really enjoy working with it.

I just miss a VHDL plugin for Atom (https://atom.io/packages/vhdl-entity-converter) which is very handy.

Putting the cursor into an entity allows to copy it as an instance, as a component, or as a set of signals (the signal of the good type for each entity port).

I would love to see it appearing in this plugin as it boosts the productivity for toplevel assembly.
Thanks
Sébastien

I usually use VS Code mostly in terms of file editing; normally I work in parallel with Vivado (a Xilinx tool used to synthesize VHDL code for their products) because currently there is no way for VS Code to identify whether an entity has been included correctly within the project, or even within a specific folder.

That being said, my idea was having a folder indexing which would be capable of reading the code and being able to identify if the component I'm trying to instantiating somewhere is either present within my path, and if it is coherent with the entity definition itself.

For example:

...
architecture rtl of myTop is

component myComponent
port (
port1: in std_logic;
port2: in std_logic;
port3: in std_logic;
port4: out std_logic
);
end component;

signal port1, port2, port3, port4: std_logic;
...

begin

i_myComp: myComponent
port map (
port1 => port1,
port2 => port2,
--port3 => port3, (this is commented out so it's not declared)
port4 => port4
);

It would be nice to identify the fact that there is no port3 associated to i_myComp.
It would be probably a bit more complicated when considering the possibility that port3 or any other port may also have a default value associated, but I guess it would be a start anyway.

Would this make sense to you @richjyoung ?

Hi

The following problem occurs when i use the stutter comments mode:
As my code is indented, i start to write my code at column 2 (two spaces characters at the begining of my line). But when i wrote '---', the VHDL extension create a comment '-----' line. But instead of ends at line 110 (which is configured as line length) the extension wrote 110 charcters '---'.

It is possible to take the start column and write only characters to reach line lenght ?

Thanks.
Best regards

Hi,

It seems there is a bug in interaction between VHDL mode and autocompletion feature of vscode.
As soon as i use a boolean operator such as 'and', 'or, etc, autocompletion stops to work.

For exmple if i write:
if foo = '0' and b..

All existing signals start with 'b' are not displayed as it should be.

Regards

OS Version: Windows 10 1809
VS Code Version: 1.33.1
Extension Version: 0.0.7

First of all, thank you for your job.
Suppose there is a signal, whose type is std_logic_vector:
signal a : std_logic_vector (15 downto 0);
Then I want to assign a constant value x"1234" to it:
a <= x"1234";
Sorry for my English. So I attach a gif:

As show before, the double quote after letter x is not auto closed.
My suggestion is add following snippet:
(snippets/vhdl.yml)

hex_std_logic_vector:
  prefix: x"
  description: x"nnnn"
  scope: source.vhdl
  body: "x\"$1\"$0"

(snippets/vhdl.json)

	"hex_std_logic_vector": {
		"prefix": "x\"",
		"description": "x\"nnnn\"",
		"scope": "source.vhdl",
		"body": "x\"$1\"$0"
	}

Result as shown below:

By the way, this issue may depend on every one's typing habits.

The signal name not displayed properly, but also, the process block is never terminated, resulting in follow up errors:

The textmate grammar used by Github also has trouble:

architecture arch of test is
    signal process_start : boolean;
begin
    process_start <= true;
end arch;

Hello,
The current library generation based on ieee prefix is pretty weak and inflexible. It would be great if it could respect either vhdl.suggestLibraryCase settings or current typing case - e.g., writing it without capitals would generate following:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

... instead of ...

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

It may be somewhat connected with #6 but this particular case was not covered in the proposed changes.

What do you think about this suggestion?

Hello,
The issue is the following:

I have a package with this record declared

type myRecord_t is record
   a : std_logic;
   b : std_logic_vector(7 downto 0);
   c : std_logic_vector(7 downto 0);
end record myRecord_t

If i want to create a signal of type myRecord_t initialized to zero in all fields i have to write

signal myInst : myRecord_t := (a => '0', b => (others => '0'), c => (others => '0'));

or more briefly

signal myInst : myRecord_t := (a => '0', b|c => (others => '0'));

In the latter case, 'b' and 'c' have different colors.

Hi! Thank you for this great (and up-to-date) extension, keep up the good work!

I'd like to propose two features coming from the great VHDL-mode integrated in Emacs, the "Stuttering mode" and the "Header insertion".
Will it be possible to see them integrated in a next plug-in release?

I'll directly copy-paste the description you can find in the docs:

HEADER INSERTION:
A file header can be inserted by ‘C-c C-t C-h’. A file footer
(template at the end of the file) can be inserted by ‘C-c C-t C-f’.
See customization group ‘vhdl-header’.

This is what (roughly) an inserted header looks like:

-------------------------------------------------------------------------------
-- Title      : <title_name_here>
-- Project    : <project_name_here>
-------------------------------------------------------------------------------
-- File       : <file_name_here>.vhd
-- Author     : <author_name>
-- Company    : <company_name_here>
-- Created    : 2019-03-08
-- Last update: 2019-03-09
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: <insert_description_here>
-------------------------------------------------------------------------------
-- Copyright (c) 2019 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2019-03-08  1.0    <auth>    Created
-------------------------------------------------------------------------------

STUTTERING:
Double striking of some keys inserts cumbersome VHDL syntax elements.
Stuttering can be disabled (enabled) by typing ‘C-c C-m C-s’ or by
option ‘vhdl-stutter-mode’. Enabled stuttering is indicated by ‘/s’ in
the mode line. The stuttering keys and their effects

;;   -->     " : "            [   -->  (          --    -->  comment
;;;  -->     " := "          [[  -->  [          --CR  -->  comment-out code
..   -->     " => "         ]   -->  )          ---   -->  horizontal line
,,   -->     " <= "         ]]  -->  ]          ----  -->  display comment
==   -->  " == "          ''  -->  \"

Thanks!

Hi,

I don't kown if it is a missing feature, a current limiation or a bad configuration in my vscode but is there a way to have an automatic indentation for some specific construction ?

For example:
when i start to write:

if ( a = '1' ) then
  b = '0';
end if;

It would be nice that automatically vscode indent the line when i press 'enter'. And removes indentataion when i write 'end if'.

Thanks for all of your work on this extenstion.

Hi,
when declaring multiple signals at once, like in the example below, the last signal name has a wrong color.

signal a,
       b,
       c : std_logic := '0';

Hello Rich,

Thanks for, unlike many extensions out there, maintaining your vscode extension.
I have been using its grammar for some time now, found a few bugs, and would like to help fixing these. I thought it is best to post an issue for each of them, if you would like to get them together, please let me know.

This first has pull request #22 open to fix it.

Something similar happens during process definition. If i write a statement like

ProcessName: process(Clk)

If I write begin after newline, the indent is automatically decreased by one.

Originally posted by @jacopobelli in #23 (comment)

If a statement like
type sample_buffer_t is array (0 to 7) of std_logic_vector(6 downto 0);
or
type state_t is (LOAD, FIND_COLLECT, FIND_XOR, ADJ, ADJ_PAUSE);
is written, the indent is increased by one when it shouldn't be.

Hello,

I updated to 1.0.3 and all signals names suggestions disappeared. I solved the problem for now re-installing version 1.0.0.

Regards

Hello @richjyoung! 👋

First, thank you for developing this vscode extension! ❤️ It seems to be the best vscode VHDL extension to date! 👍

Now, I would really appreciate adding the support for generating std_ulogic_vector snippets just like with std_logic_vector. Needless to say that std_ulogic should be generally preferred, with the exception of creating buses.

As a prefix I would suggest to use stdu. I do not mind if it would hint std_logic_vector all the way up to std and then, with typing u, it would switch to std_ulogic_vector.

I have briefly inspected the code and I suspect that the vhdl.yml file is the only one to modify. I can try to prepare a PR for that.

What do you think? 🤔

Hi,

First of all, thank you for the great job you've done on this extension. It is very pleasant to use it when you develop in VHDL.

I've a question:
Is it possible to have some features similar to those in th vhdl plugin in SublimeText ? Especially the fonctionality which allows us to copy a module port declaration and past it as signal, or component.

Hi there, I have a pull request ready for the feature reported in the issue title. Let me know if you're interested.

Hello for the third time! 😄

The current letter case of code completion hints does not always match with the letter case of actually applied hints. In other words, the code completion hints do not respect vhdl.suggestAttributeCase, vhdl.suggestLibraryCase and vhdl.suggestPackageCase settings and they have fixed letter case.

This one is not a serious issue to be honest but it decreases the overall user experience a bit. Hence, would it be feasible to make the code completions respect the mentioned settings? Or is there too much overhead in that? 🤔

The settings I used are probably obvious but just for the sake of completeness:

"vhdl.suggestAttributeCase": "upper"
"vhdl.suggestLibraryCase": "lower"
"vhdl.suggestPackageCase": "lower"

Again, the github grammar is not much better here, although it is less visible due to the poor contrast (look closely at the 'Y' ):

architecture arch of test is
    -- Suggestion: format all literals the same, independent
    -- where they occur.
    type my_logic is (
        '0',
        'x',
        'Y',
        'Z',
        fuzzy_state);

    constant my_logic_constant : my_logic := 'Z';
    constant my_fuzzy_logic_constant : my_logic := fuzzy_state;
begin
end arch;

It would be nice to have an option to insert snippets with uppercase keywords.

hi.
while shortcut for the brackets is enabled, and You press “ [ “ Open Square Brackets, In order to replace by “ ( “ Open Round brackets, The shortcut is working but both: “ ( “ and “ [ “ are writing... and You must to remove the second bracket “ [ “ And continue your coding. This issue makes the shortcuts less efficient.