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QEMU with RISC-V (RV64G, RV32G) Emulation Support

Makefile 0.25% C 91.46% C++ 2.72% Shell 1.31% Haxe 0.48% Objective-C 0.23% Assembly 0.44% Python 2.80% NSIS 0.01% Perl 0.30% Emacs Lisp 0.01% GLSL 0.01% GDB 0.01%

riscv-qemu's Introduction

The RISC-V QEMU Port is Upstream

The RISC-V QEMU port is developed in the upstream QEMU repository. You may be more interested in the official releases.

riscv-qemu's People

Contributors

Stargazers

Watchers

Forkers

liuzhiping gzh19890524 docrjp southerngs lluixhi genkilife 8l cambridgehackers jameyhicks 32bitmicro sorear martinmaas aneesh-neelam bkoppelmann cyclyy randysuen brucehoult kito-cheng zhkai cmchao miet-riscv-workgroup jrrk hongyunnchen amesianx qshan wabashos aakarsh fernandez-miguel-a poweihuang17 moneytech ygemici jvarghe9998 disasm xorgy umitsamima pinpiew michaeljclark stlcours gorkemmulayim shawnanastasio microsemi-soc-ip mcnamarad1971 axl-zhang preacle hstogether davidlt nealscarffery salewski akashgj terudeca darius-bluespec iwashi-project heshamelmatary shlevy mit-sanctum huangwei mandarcthorat kchhero twd2 msuozzo sifive subashp handsome3163 sl33k yosukezith devopsmi jixianghu lucashmorais exokortex jaskon139 innothoughts embecosm charlesxu wujiu913 zmole945 dayeol 511-tangs sebhub charims bhupesh-sharma hautezwei curacaoyang konkanello nwf johnfrees rbarraud jim-wilson cartesi-corp algochips ethercflow keystone-enclave shishu8385 wxjstz lukasauer songwenbin247 atishp04 pulp-platform gauravdesale lu-ping myamada9999

riscv-qemu's Issues

master fails to boot on OSX 10.10.5 since 7ecbff9

Before:

$$ git clean -dfx
$$ git log -1
commit 80cc834fabca5dc10b9931432f85aa3bfea68b6d
Author: Sagar Karandikar <[email protected]>
Date:   Wed Dec 23 21:39:07 2015 +0000

    add ability to singlestep with -singlestep

    can also print regs,inst with -d in_asm,cpu
$$ git submodule update --init pixman
$$ ./configure --target-list=riscv-softmmu >&config.log
$$ make -j4 >&make.log
$$ curl -s -o vmlinux.2 http://riscv.org/qemu/vmlinux
$$ curl -s -o root.bin.2 http://riscv.org/qemu/root.bin
$$
$$ ./riscv-softmmu/qemu-system-riscv -m 2048M -hda root.bin.2 -kernel vmlinux.2 -nographic

(process:72608): GLib-WARNING **: gmem.c:482: custom memory allocation vtable not supported
[    0.000000] Linux version 3.14.15-g4073e84-dirty (skarandikar@a8) (gcc version 4.9.2 (GCC) ) #4 Sun Jan 11 07:17:06 PST 2015

After:

$$ git clean -dfx
$$ git log -1
commit ce46c3922ab83702d1f64d87daeb5dd7094bd89d
Author: Sagar Karandikar <[email protected]>
Date:   Mon Feb 1 15:41:47 2016 -0800

    update to softfloat from spike 853391c2bb814451ad88b8dbff2aec8616fc6a12
$$ ./configure --target-list=riscv-softmmu >&config.log
$$ make -j4 >&make.log
$$ curl -s -o vmlinux https://www.eecs.berkeley.edu/~skarandikar/host/qemu/vmlinux
$$ curl -s -o rootfs.ext2 https://www.eecs.berkeley.edu/~skarandikar/host/qemu/rootfs.ext2
$$ curl -s -o bbl https://www.eecs.berkeley.edu/~skarandikar/host/qemu/bbl
$$ md5 bbl vmlinux rootfs.ext2
MD5 (bbl) = 627095c408053843ef53cfe1245738c5
MD5 (vmlinux) = fa21453823b3bcf2766e561ef91b7009
MD5 (rootfs.ext2) = 03a3f284572f89a5877461bd9b1f0775
$$ ./riscv-softmmu/qemu-system-riscv -m 2048M -kernel bbl -hda rootfs.ext2 -append vmlinux -nographic

(process:70059): GLib-WARNING **: gmem.c:482: custom memory allocation vtable not supported
reading device tree at 0x0000000080000000
at 0x0000000000000000, found 2048 MiB of memory
at 0x0000000080001000, found hart 0
INVALID close fd: -1. only 3 allowed
Did you supply the right kernel using -append?
$$

Minor make clean issue

This is pretty trivial, but line 269 in the Makefile uses rm instead or rm -f, so I get prompted to override write protections for five files upon each make clean.

Floating-point exception flags not set correctly?

This gfortran test in the GCC test suite fails on QEMU but passes on Spike: https://github.com/riscv/riscv-gcc/blob/riscv-gcc-7/gcc/testsuite/gfortran.dg/ieee/ieee_1.F90#L58

It seems likely that it's a problem with setting the floating-point exception flags in fflags/fcsr, because the test is expecting the Overflow/Inexact to be set, but the program reports that no flags are set.

Update target-riscv/TODO

Hi,
I am interested with helping port RISC V to QEMU. I am just learning about RISC V architecture and ISA in my attempt to learn more about different computer architecture.

I have some experience working on QEMU professionally,
https://git.qemu.org/qemu.git/?p=qemu.git&a=search&h=HEAD&st=author&s=Farhan+Ali,
and I would like to help anyway I can to learn more :)

Nonzero retval from testing script

Running hacking_files/run_riscv_tests.py, getting error for every test:

../riscv32-softmmu/qemu-system-riscv32 -m 3840M -kernel /media/psf/work/riscv/risc_v/test-suite/isa/rv32ui-v-ori -nographic
NONZERO RETVAL for rv32ui-v-ori
139

Running QEMU manually for any test results in segfault

implement TSR, TW and TVM for privileged ISA v1.10

The TVM (Trap Virtual Memory) bit supports intercepting supervisor virtual-memory management
operations. When TVM=1, attempts to read or write the satp CSR or execute the
SFENCE.VMA instruction while executing in S-mode will raise an illegal instruction exception.
When TVM=0, these operations are permitted in S-mode. TVM is hard-wired to 0 when S-mode
is not supported.

The TW (Timeout Wait) bit supports intercepting the WFI instruction (see Section 3.2.3). When
TW=0, the WFI instruction is permitted in S-mode. When TW=1, if WFI is executed in S-mode,
and it does not complete within an implementation-specifi c, bounded time limit, the WFI
instruction causes an illegal instruction trap. The time limit may always be 0, in which case WFI
always causes an illegal instruction trap in S-mode when TW=1. TW is hard-wired to 0 when
S-mode is not supported.

The TSR (Trap SRET) bit supports intercepting the supervisor exception return instruction, SRET.
When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction
exception. When TSR=0, this operation is permitted in S-mode. TSR is hard-wired to 0 when
S-mode is not supported.

Mask mie/mip fields depending on whether S mode is enabled (misa.S)

When S-mode (misa.S) is not present, writes to mip/mip.SEIP/SSIP/STIP and mie/sie.SEIE/SSIE/STIE need to be masked.

U-mode interrupts and the N-extension are not currently implemented, so these fields are already masked

hacking_files/vmlinux out of date?

Hi,

I believe that the content of hacking_files/vmlinux is now out of date.

I tried to compile my binaries and run them under qemu (qemu updated and recompiled yesterday, and binaries also recompiled with the new ABI unless I made some mistake); but the binaries won't run when I use the kernels in hacking_files/vmlinux to run inside qemu (I can paste the error when starting the binaries, if it's of any use).

I tried to compile a kernel myself, but qemu or the kernel segfault before printing anything useful, I don't know exactly what's wrong either.

So it would be great if these kernels could be updated to run the latest binaries, so I least people can see if their programs and compiled binaries are working fine.

Cheers and thanks.

Can't remote debug program with qemu user mode

Qemu hash = 8e35f13

GNU Toolchain hash = riscv-collab/riscv-gnu-toolchain@8000750

$ riscv64-unknown-linux-gnu-gcc ~/hello.c -o hello.rv64 -static -g3
$ qemu-riscv64 -g1234 hello.rv64
# In another terminal
$ riscv64-unknown-linux-gnu-gdb hello.rv64 
GNU gdb (GDB) 7.11.50.20160803-git
Copyright (C) 2016 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.  Type "show copying"
and "show warranty" for details.
This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-linux-gnu".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<http://www.gnu.org/software/gdb/bugs/>.
Find the GDB manual and other documentation resources online at:
<http://www.gnu.org/software/gdb/documentation/>.
For help, type "help".
Type "apropos word" to search for commands related to "word"...
Reading symbols from hello.rv64...done.
(gdb) target remote :1234
Remote debugging using :1234
Ignoring packet error, continuing...
Ignoring packet error, continuing...
Ignoring packet error, continuing...

compilation error (undefined functions) unless --disable-werror

  CC    riscv-softmmu/cpu-exec-common.o
In file included from /archive/toolchain/riscv-qemu/include/qemu-common.h:53:0,
                 from /archive/toolchain/riscv-qemu/tcg/tcg.c:39:
/archive/toolchain/riscv-qemu/target-riscv/cpu.h:434:13: error: inline function 'cpu_riscv_tlb_flush' declared but never defined [-Werror]
 inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global);
             ^
In file included from /archive/toolchain/riscv-qemu/cpu-exec.c:20:0:
/archive/toolchain/riscv-qemu/target-riscv/cpu.h:434:13: error: inline function 'cpu_riscv_tlb_flush' declared but never defined [-Werror]
 inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global);
             ^
In file included from /archive/toolchain/riscv-qemu/include/qemu-common.h:53:0,
                 from /archive/toolchain/riscv-qemu/translate-all.c:33:
/archive/toolchain/riscv-qemu/target-riscv/cpu.h:434:13: error: inline function 'cpu_riscv_tlb_flush' declared but never defined [-Werror]
 inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global);
             ^
In file included from /archive/toolchain/riscv-qemu/include/qemu-common.h:53:0,
                 from /archive/toolchain/riscv-qemu/translate-common.c:20:
/archive/toolchain/riscv-qemu/target-riscv/cpu.h:434:13: error: inline function 'cpu_riscv_tlb_flush' declared but never defined [-Werror]
 inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global);
             ^
In file included from /archive/toolchain/riscv-qemu/cpu-exec-common.c:21:0:
/archive/toolchain/riscv-qemu/target-riscv/cpu.h:434:13: error: inline function 'cpu_riscv_tlb_flush' declared but never defined [-Werror]
 inline void cpu_riscv_tlb_flush (CPURISCVState *env, int flush_global);
             ^
cc1: all warnings being treated as errors
/archive/toolchain/riscv-qemu/rules.mak:57: recipe for target 'translate-common.o' failed

Enable SV48

Testfix in a94c1b4

Is it possible to use more than one block device?

Hi,

I tried to use more than one -drive, or -cdrom or -hdb, but it doesn't seem to work.

Is it possible to have more than one block device at all?

Hardware Performance Monitor Privileged V1.10 Support

My riscv-qemu HEAD is 05e0ed

The read access logic for CRS_INSTRET, and CSR_CYCLE are priv-1.9.1 only, though HPM CSRs for both priv-1.9.1 and priv-1.10 are there.

Can't use sifive-uart device to output on host console.

I can't understand why my hello-world bare-metal program dont prints characters on screen.
I try to write charecters consequentally to memory with base address of uart (0x40002000) but i doesnt see anything.
Is it perform of uart device and output impossible at all, and if i want to output something i must create uart device on my own? or i setup something inattentively?
excluded crt.s ld script
main.c

  volatile unsigned int * const UART0DR = (unsigned int *)0x40002000;                                 
                                                                                                      
  void print_uart0(const char *s)                                                                     
  {                                                                                                   
       while(*s != '\0') {                                                                            
            *UART0DR = (unsigned int)(*s);                                                            
              s++;                                                                                     
       }                                                                                              
  }                                                                                                   
                                                                                                      
  int main()                                                                                          
 {                                                                                                   
      print_uart0("Hello world!\n");                                                                  
      return 0;                                                                                       
  }

shell command:

qemu-system-riscv32 -m 2048M -M sifive -kernel prog.elf -nographic

Remove cmpxchg and cmpxchg64 syscalls

cmpxchg and cmpxchg64 syscalls have been removed from the Linux ABI as the A extension is now mandatory for the Linux/UNIX platform. They can be removed from target-riscv/user_syscall.c. See https://github.com/riscv/riscv-qemu/blob/07146abe22e5ea5948fda5d511fd1fd228e196fa/target-riscv/user_syscall.c

Got error when installing riscv-qemu

Hi,
I installed riscv-qemu as README.md. When I do "make" I got this error:

/root/riscv-qemu/hw/riscv/htif/htif.c:176:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘hwaddr’ [-Werror=format=]
     printf("Invalid htif register address %016lx\n", (uint64_t)addr);

After i commented it, i got new error:

/root/riscv-qemu/target-riscv/op_helper.c:482:34: error: expected ‘)’ before ‘a’
 return (int64_t)((__int128_t)a*b >> 64);
/root/riscv-qemu/target-riscv/op_helper.c:481:14: error: unused variable ‘b’ [-Werror=unused-variable]
 uint64_t b = arg2;
/root/riscv-qemu/target-riscv/op_helper.c:480:13: error: unused variable ‘a’ [-Werror=unused-variable]
 int64_t a = arg1;

My os is: ubuntu 3.19.0-15-generic. My compiler is gcc-4.9.2
I will really appreciate it if you can offer some help!

SIGCHLD delivery problem

Test program:

#include <stdlib.h>
#include <unistd.h>
#include <signal.h>
#include <sys/wait.h>

void chld(int signo) {
        write(2,"sigchld delivered\n",18);
}

int main() {
        struct sigaction cld_sa = {};
        cld_sa.sa_handler=chld;
        sigaction(SIGCHLD, &cld_sa,0);
        system("echo system child");
        if (fork() == 0) { write(2,"fork child\n",11); exit(0); }
        int stat; wait(&stat);
        return 1;
}

Correct output:

built/run natively (x86_64)
built i386 and run under qemu-i386 from this repository

system child
sigchld delivered
fork child
sigchld delivered

Incorrect output, seen when built riscv64 and run under qemu-riscv64:

system child
sigchld delivered
fork child

Apparently we're coming out from system() with SIGCHLD still blocked.

(this is a C translation and golfing of coprocess.sh from the ksh93 test suite, which hangs in a qemu-riscv64 architecture emulation container)

scripts/qemu-binfmt-conf.sh does not register riscv

If the appropriate magic string for riscv elf binaries is added, and pointed to the installed qemu-riscv{32,64} binary, then we can run linux riscv binaries at the command line as if they were x86 binaries.

risc-v tests success check

Wanted to know, what is condition of passing riscv-tests? Couldn't find where is the checker for some value etc. in qemu.

"Register 3921 is not available" when debugging https://github.com/schoeberl/cae-examples on qemu

https://github.com/schoeberl/cae-examples provides a bare-metal test for riscv.

Running it with:

qemu-system-riscv64 -nographic -S -s -kernel test

And stepping it through gdb with:

riscv64-unknown-elf-gdb test
target remote localhost:1234
ni
ni

Gives the message "Register 3921 is not available".
Note that the test proceeds normally without any issues though.

GDB issue

That Tim mentioned here:
riscvarchive/riscv-binutils-gdb#25

riscv-qemu hangup

hi,

When I run riscv-linux on riscv-qemu, sometime linux kernel hangup, I found it looks qemu does not execute instruction. the backtrace of riscv is below:
#0 0x00007fc2f67977d1 in __GI_ppoll (fds=0x5558d5fe66d0, nfds=5, timeout=, timeout@entry=0x7ffccbb0f920, sigmask=sigmask@entry=0x0) at ../sysdeps/unix/sysv/linux/ppoll.c:50
#1 0x00005558d42690b9 in ppoll (__ss=0x0, __timeout=0x7ffccbb0f920, __nfds=, __fds=) at /usr/include/x86_64-linux-gnu/bits/poll2.h:77
#2 qemu_poll_ns (fds=, nfds=, timeout=timeout@entry=1000000000) at /home/janboe/riscv/freedom-u-sdk/riscv-qemu/qemu-timer.c:325
#3 0x00005558d4268aea in os_host_main_loop_wait (timeout=1000000000) at /home/janboe/riscv/freedom-u-sdk/riscv-qemu/main-loop.c:252
#4 main_loop_wait (nonblocking=) at /home/janboe/riscv/freedom-u-sdk/riscv-qemu/main-loop.c:506
#5 0x00005558d410db2c in main_loop () at /home/janboe/riscv/freedom-u-sdk/riscv-qemu/vl.c:1947
#6 main (argc=, argv=, envp=) at /home/janboe/riscv/freedom-u-sdk/riscv-qemu/vl.c:4662

My riscv-qemu HEAD is cd2c21d

Does anyone meet same issue?

Thanks

Janboe

Implement riscv_flush_icache syscall

riscv_flush_icache architecture specific syscall has been added to riscv-linux. This needs to be implemented in target-riscv/user_syscall.c. See https://github.com/riscv/riscv-linux/blob/riscv-next/arch/riscv/kernel/sys_riscv.c#L66-L79

Not found bblvmlinuxinitramfs_v1.10

According README, we can download bblvmlinuxinitramfs_v1.9 and bblvmlinuxinitramfs_v1.9.1 but I could not get bblvmlinuxinitramfs_v1.10.

Is there any source to generate specific versions of bblvmlinuxinitramfs ?

Thanks !

riscv-qemu does not compile

Hey, the build fails with this (https://pastebin.com/iZvGG9YP) error message. What am i doing wrong ?

ERROR: glib-2.22 gthread-2.0 is required to compile QEMU

Hello,

The configure gives the following error.


alpha@alpha-VirtualBox:~/zephyr/riscv-qemu$ ./configure --target-list=riscv64-softmmu,riscv32-softmmu --prefix=/opt/riscv

ERROR: glib-2.22 gthread-2.0 is required to compile QEMU

I have build-essential, libc6-dev and when I install apt-get install libglib2.0-dev zlib1g-dev, I get the broken packages error.

And when I install gcc libc6-dev pkg-config bridge-utils uml-utilities zlib1g-dev libglib2.0-dev autoconf automake libtool libsdl1.2-dev, I get the following message:

Reading package lists... Done
Building dependency tree       
Reading state information... Done
autoconf is already the newest version.
automake is already the newest version.
gcc is already the newest version.
libtool is already the newest version.
pkg-config is already the newest version.
pkg-config set to manually installed.
zlib1g-dev is already the newest version.
libc6-dev is already the newest version.
Some packages could not be installed. This may mean that you have
requested an impossible situation or if you are using the unstable
distribution that some required packages have not yet been created
or been moved out of Incoming.
The following information may help to resolve the situation:

The following packages have unmet dependencies:
 libglib2.0-dev : Depends: libglib2.0-0 (= 2.40.0-2) but 2.40.2-0ubuntu1 is to be installed
                  Depends: libglib2.0-bin (= 2.40.0-2)
                  Depends: libpcre3-dev (>= 1:8.31) but it is not going to be installed
 libsdl1.2-dev : Depends: libsdl1.2debian (= 1.2.15-8ubuntu1) but 1.2.15-8ubuntu1.1 is to be installed
                 Depends: libcaca-dev but it is not going to be installed
                 Depends: libglu1-mesa-dev but it is not going to be installed or
                          libglu-dev
                 Depends: libpulse-dev but it is not going to be installed
                 Depends: libxext-dev but it is not going to be installed
E: Unable to correct problems, you have held broken packages.

Could you please tell me what I'm missing ?

Thank you

gitsubmodules use git protocol

IT departments are sometimes evil and don't open up the ports necessary to use the git:// protocol. All of the submodules support cloning via http or https. It would be nice to have the submodules setup to use those protocols which are normally open.

unable to build on Fedora 23

CC vl.o
vl.c: 在函数‘main’中:
vl.c:2972:5: 错误：‘g_mem_set_vtable’ is deprecated [-Werror=deprecated-declarations]
g_mem_set_vtable(&mem_trace);
^
In file included from /usr/include/glib-2.0/glib/glist.h:32:0,
from /usr/include/glib-2.0/glib/ghash.h:33,
from /usr/include/glib-2.0/glib.h:50,
from vl.c:59:
/usr/include/glib-2.0/glib/gmem.h:357:7: 附注：在此声明
void g_mem_set_vtable (GMemVTable vtable);
^
cc1：所有的警告都被当作是错误
/home/yaofei/src/riscv/riscv-qemu/rules.mak:33: recipe for target 'vl.o' failed
make: ** [vl.o] Error 1

Implement support for IEEE 754-201x minimumNumber/maximumNumber

These two patches were dropped because softfloat was under change in upstream: 74d08bb 19861c3

The change to the minmax macro needs to be forward ported to the latest softfloat code which now may be a static inline function instead of a macro. This will fix fmin/fmax failures in riscv-tests.

RVC not supported

Wow! Surprised me, five years after RVC was proposed. Could not understand why my compiled code didn't run.

Surely can't be hard to do a quick, low performance (pseudocode):

if ((ins32 & 0x3) != 0x3){
   ins32 = decode_rvc_to_rv(ins32);
   pc -= 2;
}

... and change the PC alignment checking.

qemu-system-riscv32 crashes when passed a 64-bit ELF

crash when providing 64-bit ELF to qemu-system-riscv32

lldb ./riscv32-softmmu/qemu-system-riscv32 
(lldb) run -nographic -machine spike_v1.10 -kernel bin/probe 
Process 45719 launched: '../riscv-qemu/riscv32-softmmu/qemu-system-riscv32' (x86_64)
Process 45719 stopped
* thread #1, queue = 'com.apple.main-thread', stop reason = EXC_BAD_ACCESS (code=1, address=0x7fffbf01b899)
    frame #0: 0x00007fff58e836b7 libsystem_platform.dylib`_platform_strcmp + 23
libsystem_platform.dylib`_platform_strcmp:
->  0x7fff58e836b7 <+23>: movzbq (%rsi), %r8
    0x7fff58e836bb <+27>: incq   %rdi
    0x7fff58e836be <+30>: incq   %rsi
    0x7fff58e836c1 <+33>: subq   %r8, %rax
Target 0: (qemu-system-riscv32) stopped.
(lldb) bt
* thread #1, queue = 'com.apple.main-thread', stop reason = EXC_BAD_ACCESS (code=1, address=0x7fffbf01b899)
  * frame #0: 0x00007fff58e836b7 libsystem_platform.dylib`_platform_strcmp + 23
    frame #1: 0x0000000100071939 qemu-system-riscv32`htif_mm_init(address_space=<unavailable>, kernel_filename=<unavailable>, irq=<unavailable>, main_mem=<unavailable>, env=<unavailable>, chr=<unavailable>) at htif.c:378 [opt]
    frame #2: 0x00000001000759ea qemu-system-riscv32`riscv_spike_board_init(machine=<unavailable>) at spike_v1_10.c:225 [opt]
    frame #3: 0x0000000100098a71 qemu-system-riscv32`qemu_main(argc=<unavailable>, argv=0x0000000008000000, envp=<unavailable>) at vl.c:4525 [opt]
    frame #4: 0x00007fff58c03145 libdyld.dylib`start + 1
    frame #5: 0x00007fff58c03145 libdyld.dylib`start + 1

The HTIF symbol code appears to unconditionally open the ELF object as 64-bit if TARGET_RISCV64 is defined and as a 32-bit ELF object if TARGET_RISCV64 is not defined. elf_open and elf_open32 probably need to check the magic and bitwidth of the ELF object.

HTIFState *htif_mm_init(MemoryRegion *address_space,
           const char *kernel_filename, qemu_irq irq, MemoryRegion *main_mem,
           CPURISCVState *env, CharDriverState *chr)
{
    uint64_t fromhost_addr = 0;
    uint64_t fromhost_size = 0; /* for pk vs tests */
    uint64_t tohost_addr = 0;
    uint64_t tohost_size = 0; /* for pk vs tests */

    /* get fromhost/tohost addresses from the ELF, as spike/fesvr do */
    if (NULL != kernel_filename) {
#if defined(TARGET_RISCV64)
        Elf_obj *e = elf_open(kernel_filename);
#else
        Elf_obj32 *e = elf_open32(kernel_filename);
#endif

        const char *fromhost = "fromhost";
        const char *tohost = "tohost";

#if defined(TARGET_RISCV64)
        Elf64_Sym *curr_sym = elf_firstsym(e);
#else
        Elf32_Sym *curr_sym = elf_firstsym32(e);
#endif
        while (curr_sym) {
#if defined(TARGET_RISCV64)
            char *symname = elf_symname(e, curr_sym);
#else
            char *symname = elf_symname32(e, curr_sym);
#endif

            if (strcmp(fromhost, symname) == 0) {
                /* get fromhost addr */
                fromhost_addr = curr_sym->st_value;
                fromhost_size = curr_sym->st_size; /* this is correctly set to 8
                                                      by pk */
            } else if (strcmp(tohost, symname) == 0) {
                /* get tohost addr */
                tohost_addr = curr_sym->st_value;
                tohost_size = curr_sym->st_size; /* this is correctly set to 8
                                                    by pk */
            }
#if defined(TARGET_RISCV64)
            curr_sym = elf_nextsym(e, curr_sym);
#else
            curr_sym = elf_nextsym32(e, curr_sym);
#endif
        }
    }

Fix AMO handling (should cause store faults)

To match riscv-software-src/riscv-isa-sim@bf8d2b7

update performance counter CSRs

Using the newest riscv-gcc to build bbl and linux can not run in riscv-qemu, since the performance counter definitions in riscv-qemu are not matched to the code generated by riscv-gcc.

Hangs and prints "main-loop: WARNING: I/O thread spun for 1000 iterations"

With riscv-qemu from commit bfd1ee7 (29th of Dec of 2014) and using the kernel currently provided as a download from the website (version 3.14.15-g4073e84-dirty (skarandikar@a8)), the emulation seems to stop after printing this message:

main-loop: WARNING: I/O thread spun for 1000 iterations

Sometimes it happens very early, other times takes hours before this happens.

When that happens, I am able to quit with "ctrl-a x", but not to cancel running programs with "ctrl-c" nor to type new commands if this happens at the shell prompt.

This is possibly a bug in riscv-linux instead of riscv-qemu. Sadly I cannot provide any useful information, except possibly a backtrace of qemu-system-riscv when this happens, if you think that it's useful.

Reg. pixman folder update

$git submodule update --init pixman

Cloning into 'pixman'...
fatal: unable to connect to anongit.freedesktop.org:
anongit.freedesktop.org[0: 131.252.210.161]: errno=Connection refused
anongit.freedesktop.org[1: 2610:10:20:722:a800:ff:fe24:61cf]: errno=Network is unreachable

Clone of 'git://anongit.freedesktop.org/pixman' into submodule path 'pixman' failed

Can you tell the alternative way to update pixman submodule

Cannot allocate Memory

When I boot the linux kernel with qemu, it just reminds me that

shore@ubuntu32:~/riscv-qemu$ ./riscv32-softmmu/qemu-system-riscv32 -nographic -kernel /home/shore/riscv/riscv32-unknown-elf/bin/bbl -drive file=/home/shore/linux-4.6.2/root.bin,format=raw -m 512M
qemu-system-riscv32: cannot set up guest memory 'riscv_spike_board.ram': Cannot allocate memory

Actually, the memory of my machine is 4GB. I cannot believe that it is because the memory is not adequate. I mean that the 32bit OS can access 4GB memory at most, the OS of my computer is

Linux ubuntu32 4.4.0-31-generic #50~14.04.1-Ubuntu SMP Wed Jul 13 01:06:37 UTC 2016 i686 i686 i686 GNU/Linux

Actually, the bbl is built according to https://github.com/riscv/riscv-pk/tree/master, except that I modify the configuration because I am running a 32bit Machine

../configure --prefix=$RISCV --host=riscv32-unknown-linux-gnu --enable-32bit --with-payload=/home/shore/linux-4.6.2/vmlinux

And maybe i should point out the vmlinux is built according to https://github.com/Technolution/riscv-linux/tree/priv-1.9, the drive file system is build according to the https://github.com/riscv/riscv-tools#creating-root-disk

Anyone knows what's wrong with my procedure?

tb_flags and mmu_index

Two commits from my tree have gone missing during the change of administration:

sorear/riscv-qemu@a038a287
sorear/riscv-qemu@30c9f4fc

One of these is a correctness fix; basically, gen_intermediate_code needs to not use any information from the CPUState that isn't included in tb_flags. The current code is mixing up translations generated in different privilege and ISA states, which caused all Go executables to crash, and will cause more problems with mixed-ISA cores.

How do we proceed from here? @michaeljclark do you understand the issues involved in these patches well enough to proceed, or shall I try to redo them on the upstreaming branch? I don't think this needs to be an upstreaming blocker, although it was noticed.

riscv-tests for QEMU

Any test from riscv-tests faults in QEMU with ILLEGAL INST.
Readme says I should use ones from https://github.com/arsv/riscv-qemu-tests repo for user-mode build. Is it correct that qemu-user-mode cannot run riscv-tests binaries?

"Unassigned address called" error running latest riscv-linux

I compiled the latest riscv gcc cross compiler using a Linux x86 VM and used it to compile the latest riscv-linux kernel, assemble a root image using busy box, etc.

I can run the kernel, root image and Berkeley Boot Loader with the spike simulator like this:
spike +disk=root.bin bbl vmlinux

However, when I run the same kernel and root image using riscv-qemu with the following arguments I get an error (shown below):
qemu-system-riscv -hda root.bin -kernel vmlinux -nographic

Output shows the following and emu quickly terminates:
unassigned address was called?
with addr: FFFFFFFFFFFFFFD8
not implemented for riscv

The same version of riscv-qemu can run the pre-built vmlinux and root.bin provided as downloads from the README.md.

does U500 UART is incompatible with E310 UART?

@sorear
It looks like the SiFive U500 Coreplex UART model (introduced by 896ef7a) is incompatible with SiFive E310 UART because it uses different register layout (please see E310 register layout in
https://github.com/sifive/freedom-e-sdk/blob/master/bsp/include/sifive/devices/uart.h and in
https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/uart/UARTCtrlRegs.scala).

If this incompatibility is intentional and U500 uses it's own UART IP-block then we have to rename U500 UART model in qemu code.
If U500 uses the same UART IP-block as E310 does then we have too fix SiFive UART model in qemu code.

Compilation error with target "riscv-linux-user"

  CC    riscv-linux-user/exec.o
cc1: warning: /archive/toolchain/riscv-qemu/linux-user/riscv: No such file or directory [-Wmissing-include-dirs]
In file included from /archive/toolchain/riscv-qemu/linux-user/qemu.h:18:0,
                 from /archive/toolchain/riscv-qemu/exec.c:44:
/archive/toolchain/riscv-qemu/linux-user/syscall_defs.h:11:24: fatal error: syscall_nr.h: No such file or directory
compilation terminated.

Unable to build on MacOS X Yosemite.

Please see transcript below for how I reproduced the problem:

$ ./configure --target-list=riscv-softmmu --prefix=/Volumes/workspace/opt/riscv                                                                                                                                                                                                                                

ERROR: pkg-config binary 'pkg-config' not found

$ brew install pkg-config                                                                                                                                                                                                                                                                                      Warning: pkg-config-0.28 already installed

What is the biggest difference between qemu and spike?

Hello.

I want to modify the risc-v microArchitecture(Add Instruction.. or shadowstack implementation)

I was wondering while I was working on it.

Dir : riscv-qemu/hw/riscv

sifive_board.c (U500, sifive)
riscv_board.c (Generic board, spike)

"sifive_board.c" seem to emulate the vc707 board (sifive)

So, "riscv_board.c" is called Generic board and is marked as spike.
What does spike mean here?

and What is the biggest difference between qemu and spike?

Is spike also a virtual peripheral(H/W) implemented in S/W and can emulate it?

Move test scripts into a separate repo

The stuff from hacking_files is not going upsteam anyway, tests like that are not a part of common qemu codebase, but it's very important to have them organized and easily available for anyone willing to do any work on riscv-qemu.

And I think the new repo would become much more useful with reasonably generic build scripts. So that for instance one could pull the repo and run "make; make test" with only riscv64-unknown-elf toolchain and qemu-system-riscv64 in path, and with no other assumptions. This would naturally imply no hard-coded paths in the scripts.

The repo should probably look like riscv-tools, riscv-gnu-toolchain, i.e. build scripts + submodule for riscv-tests, and possibly riscv-linux once it gets that far.

Nonderministic failures in "git fsck" on the Fedora/qemu-user test environment

By far the most common outcome:

[root@sorear6 double-conversion]# /usr/libexec/git-core/git-fsck 
Checking object directories: 100% (256/256), done.
error: packed d1c517b46b5329764feffc3ba36684f009fafa58 from .git/objects/pack/pack-fcf816a460c2c7b722e5f16b140a7c085cac60eb.pack is corrupt
Checking objects: 100% (606/606), done.

others I've seen:

[root@sorear6 double-conversion]# /usr/libexec/git-core/git-fsck 
Checking object directories: 100% (256/256), done.
error: packed 460080c50717f6805bf6b8074b7342b16ccd7efd from .git/objects/pack/pack-fcf816a460c2c7b722e5f16b140a7c085cac60eb.pack is corrupt
Segmentation fault (core dumped)

[root@sorear6 double-conversion]# /usr/libexec/git-core/git-fsck 
Checking object directories: 100% (256/256), done.
error: packed d1c517b46b5329764feffc3ba36684f009fafa58 from .git/objects/pack/pack-fcf816a460c2c7b722e5f16b140a7c085cac60eb.pack is corrupt
Checking objects: 100% (606/606), done.

[root@sorear6 double-conversion]# /usr/libexec/git-core/git-fsck 
Checking object directories: 100% (256/256), done.
error: packed d1c517b46b5329764feffc3ba36684f009fafa58 from .git/objects/pack/pack-fcf816a460c2c7b722e5f16b140a7c085cac60eb.pack is corrupt
error: packed 872eefb7e92042104705f0ece9ed62271a75f041 from .git/objects/pack/pack-fcf816a460c2c7b722e5f16b140a7c085cac60eb.pack is corrupt
Checking objects: 100% (606/606), done.

amd64 git-fsck claims the repository is fine.

Build fails on Ubuntu 14.04.5 32 bit

Should it build on 32 bit?
When I try on Ubuntu 14.04.5 LTS 32 bit the build fails.
I do this:

git clone https://github.com/riscv/riscv-qemu
cd riscv-qemu
git submodule update --init pixman
./configure --target-list=riscv32-softmmu --prefix=riscv-qemu-install
make

and get this:

  CC    riscv64-softmmu/hw/riscv/riscv_rtc.o
/home/user/Downloads/riscv-qemu/hw/riscv/riscv_rtc.c: In function ‘timer_mm_read’:
/home/user/Downloads/riscv-qemu/hw/riscv/riscv_rtc.c:178:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘hwaddr’ [-Werror=format=]
         printf("Invalid timer register address %016lx\n", (uint64_t)addr);
         ^
/home/user/Downloads/riscv-qemu/hw/riscv/riscv_rtc.c: In function ‘timer_mm_write’:
/home/user/Downloads/riscv-qemu/hw/riscv/riscv_rtc.c:204:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 2 has type ‘hwaddr’ [-Werror=format=]
         printf("Invalid timer register address %016lx\n", (uint64_t)addr);
         ^
cc1: all warnings being treated as errors
make[1]: *** [hw/riscv/riscv_rtc.o] Error 1
make: *** [subdir-riscv64-softmmu] Error 2

Am I doing something wrong?
Thanks.

Support for RTC in virt machine

We are currently using openrdate (e.g., rdate -s rdate.directadmin.com) in Fedora stage4 to set clock once the system boots. The time goes out-of-sync, e.g. when you close your laptop lid for the night thus requiring again to run rdate to sync it up.

It would be nice if we would have RTC in virt machine so we could use:
-rtc [base=utc|localtime|date][,clock=host|vm][,driftfix=none|slew]
see: http://qemu.weilnetz.de/doc/qemu-doc.html

This could help us avoid some simple and stupid issues when clock skew is too high.

riscv-linux master branch does not compile with specified riscv-tools -mabi=lp64 not legal option

The README.md specifies a specific version of riscv-tools, and references the master branch of riscv-linux. The master branch of riscv-linux was modified on Jan 6, 2017 to use the -mabi switch which is not compatible with the specified version of riscv-tools. Linux will not build with this configuration.
What version of riscv-linux has been verified?

QEMU RISCV generates illegal instruction on csrrw

Hello, RISCV QEMU seems unable to execute csrrw instructions. Assembly encoding seems ok to me. Thanks for the help.

ENVIRONMENT
Ubuntu 1604 docker image (reproduced on Fedora 23 native as well)

QEMU:

qemu-riscv32 --version
qemu-riscv32 version 2.11.50 (-dirty)
Copyright (c) 2003-2017 Fabrice Bellard and the QEMU Projects

commit 73406e1213ee5a0ba29e7bd1a6b232a6811dc3a3
Author: Michael Clark <[email protected]>
Date:   Wed Jan 10 18:15:45 2018 -0800

RISCV gcc:

Using built-in specs.
COLLECT_GCC=riscv32-unknown-elf-gcc
COLLECT_LTO_WRAPPER=/opt/riscv/libexec/gcc/riscv32-unknown-elf/7.0.1/lto-wrapper
Target: riscv32-unknown-elf
Configured with: /mnt/riscv/rv-tools/riscv-gnu-toolchain/ubu1604-rv32-ilp32-build/../riscv-gcc/configure --target=riscv32-unknown-elf --prefix=/opt/riscv --disable-shared --disable-threads --enable-languages=c,c++ --with-system-zlib --enable-tls --with-newlib --with-headers=/opt/riscv/riscv32-unknown-elf/include --disable-libmudflap --disable-libssp --disable-libquadmath --disable-libgomp --disable-nls --enable-checking=yes --disable-multilib --with-abi=ilp32 --with-arch=rv32imafdc 'CFLAGS_FOR_TARGET=-Os  -mcmodel=medlow'
Thread model: single
gcc version 7.0.1 20170321 (experimental) (GCC)

RISCV Clang:

/mnt/riscv/llvm_riscv_github/build/bin/clang -v -O0  -isystem /opt/riscv/riscv32-unknown-elf/include -target riscv32-unknown-elf -march=rv32imafdc csrrw.c -o csrrw.elf
clang version 7.0.0 (https://github.com/llvm-mirror/clang 43e5d26a5656cb0fec35bee609c669e429699d7d) (https://github.com/llvm-mirror/llvm 23b4612e31598d3cd3edb6fbb337d61feea3dc93)
Target: riscv32-unknown--elf
Thread model: posix
InstalledDir: /mnt/riscv/llvm_riscv_github/build/bin
 "/mnt/riscv/llvm_riscv_github/build/bin/clang-6.0" -cc1 -triple riscv32-unknown--elf -emit-obj -mrelax-all -disable-free -main-file-name csrrw.c -mrelocation-model static -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -target-feature +m -target-feature +a -target-feature +f -target-feature +d -target-feature +c -target-abi ilp32 -dwarf-column-info -debugger-tuning=gdb -v -resource-dir /mnt/riscv/llvm_riscv_github/build/lib/clang/7.0.0 -isystem /opt/riscv/riscv32-unknown-elf/include -O0 -fdebug-compilation-dir /mnt/riscv/llvm_riscv_github/local_tests/test3 -ferror-limit 19 -fmessage-length 114 -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -o /tmp/csrrw-fe7c5d.o -x c csrrw.c

Compile the following code with gcc or clang:
riscv32-unknown-elf-gcc csrrw.c -o csrrw.elf

csrrw.c:

int gI;

int main() {
 unsigned cycles = 0;
 __asm __volatile(
    "csrw 0xc00," "%[cycles]\n\t"
      :[cycles]"+r"(cycles)
  );
 for (int i=0; i<1000; i++) {
        gI += i;
 }
 //printf ("Hello World %d\n", gI);
  __asm __volatile(
    "csrr %[cycles]," "0xc00" "\n\t"
      :[cycles]"=r"(cycles)
  );
  return cycles;
}

Execute in user mode:
... rv-tools/riscv-qemu/build/riscv32-linux-user/qemu-riscv32 csrrw.elf

Output:
Illegal instruction (core dumped)

Debug Output:

``IN: main
0x0001015a:  addi            sp,sp,-32
0x0001015c:  sw              s0,28(sp)
0x0001015e:  addi            s0,sp,32
0x00010160:  sw              zero,-24(s0)
0x00010164:  lw              a5,-24(s0)
0x00010168:  csrrw           zero,cycle,a5

OUT: [size=119]
0x55d8ad76e400:  41 8b 6e ec              movl     -0x14(%r14), %ebp
0x55d8ad76e404:  85 ed                    testl    %ebp, %ebp
0x55d8ad76e406:  0f 8c 5f 00 00 00        jl       0x55d8ad76e46b
0x55d8ad76e40c:  41 8b 6e 08              movl     8(%r14), %ebp
0x55d8ad76e410:  83 c5 e0                 addl     $-0x20, %ebp
0x55d8ad76e413:  41 89 6e 08              movl     %ebp, 8(%r14)
0x55d8ad76e417:  8d 5d 1c                 leal     0x1c(%rbp), %ebx
0x55d8ad76e41a:  45 8b 66 20              movl     0x20(%r14), %r12d
0x55d8ad76e41e:  65 67 44 89 23           movl     %r12d, %gs:0(%ebx)
0x55d8ad76e423:  83 c5 20                 addl     $0x20, %ebp
0x55d8ad76e426:  41 89 6e 20              movl     %ebp, 0x20(%r14)
0x55d8ad76e42a:  8d 5d e8                 leal     -0x18(%rbp), %ebx
0x55d8ad76e42d:  45 33 e4                 xorl     %r12d, %r12d
0x55d8ad76e430:  65 67 44 89 23           movl     %r12d, %gs:0(%ebx)
0x55d8ad76e435:  83 c5 e8                 addl     $-0x18, %ebp
0x55d8ad76e438:  65 67 8b 6d 00           movl     %gs:0(%ebp), %ebp
0x55d8ad76e43d:  41 89 6e 3c              movl     %ebp, 0x3c(%r14)
0x55d8ad76e441:  41 c7 86 80 01 00 00 68  movl     $0x10168, 0x180(%r14)
0x55d8ad76e449:  01 01 00
0x55d8ad76e44c:  49 8b fe                 movq     %r14, %rdi
0x55d8ad76e44f:  8b f5                    movl     %ebp, %esi
0x55d8ad76e451:  ba 00 0c 00 00           movl     $0xc00, %edx
0x55d8ad76e456:  e8 fd 3b a9 ff           callq    0x55d8ad202058
0x55d8ad76e45b:  41 c7 86 80 01 00 00 6c  movl     $0x1016c, 0x180(%r14)
0x55d8ad76e463:  01 01 00
0x55d8ad76e466:  e9 ab db ff ff           jmp      0x55d8ad76c016
0x55d8ad76e46b:  48 8d 05 11 ff ff ff     leaq     -0xef(%rip), %rax
0x55d8ad76e472:  e9 a1 db ff ff           jmp      0x55d8ad76c018

Drop writes to satp and return 0 when misa.S is set and no MMU is present.

@aswaterman

Also s* CSRs should trap if misa.S is clear

See riscv/riscv-isa-manual#141