rtimothyedwards / caravel_openframe_project Goto Github PK

Example digital project for the Efabless Caravel "openframe" harness

License: Apache License 2.0

Makefile 3.71% C 9.15% Verilog 67.76% Assembly 0.80% Tcl 6.55% Python 12.03%

caravel_openframe_project's Issues

master spi interrupt behaviour

The current interrupt in the spi master is triggered once the interrupt is enabled. Since the condition dependent on the done signal and the done signal is asserted most of the time.

If the correct behaviour is to send interrupt after each byte write, I suggest we might add the following:

reg done_delayed; 

always @(posedge clk) 
   done_delayed <= done; 
   
assign  irq_out = irqena & done & ~done_delayed;

counter interrupts

There are 2 problems with counter interrupts.

The counter will continuously send interrupts after the count is finished. because of this condition as long as irq_ena is 1 and stop_out is 1 (happened when the counter finish couting)

This can be fixed by trigger interrupts only at the positive edge of stop_out

It's not interrupt bug but it appears while debugging interrupt. Register value_reset isn't updated with the write condition I believe it should depend on the reg_dat_we rather than reg_val_we like this part of the code

This can be fixed by replacing reg_val_we with reg_dat_we in lines 174 to 177

Missing pins in template def

The range gpio_loopback_zero[15:23] is missing in the template def file. In addition, some pins such as gpio_loopback_one[0] have two definitions. Each definition has a different location.

Needs multiple power supply connections

The example needs to demonstrate how to connect multiple supply domains together to boost the current capacity of the supply feeding the user wrapper circuit and to minimize I-R drop across the user wrapper circuit. This example project should connect together the vccd, vccd1, and vccd2 domains into a single power supply.

Wrong dimensions for `gpio_analog_pol[33]` in template def

gpio_analog_pol[33] is a met3 pin with width < met3 min width.

Select out of bounds on signal `gpio_dat_o[*]`

In the following section, in picorv32.v:

	for (i = 0; i < 32; i = i + 1) begin
	    assign gpio_all_dat_o[i] = |(gpio_dat_o[i][`OPENFRAME_IO_PADS-1:0]);
	end

[`OPENFRAME_IO_PADS-1:0] is out of bound for the 32 bus gpio_data_o[i]. I believe the intention behind the for loop was to OR all i'th bit of each PADS gpio bus. The current for loop doesn't accomplish that.

Housekeeping reset register doesn't function

Asserting the housekeeping reset register doesn't reset the CPU like caravel.

Flashing isn't working with vcs

Cocotb tests are only working with iverilog and flashing fails with VCS. After debugging I found the problem are with the ack and stb signals and that lead me to these 2 warnings

Warning-[AOUP] Attempt to override undefined parameter
/home/rady/caravel/openframe/caravel_openframe_user_project//verilog/rtl/picosoc.v, 736
Attempting to override undefined parameter "ADR_MASK", will ignore it.

Warning-[AOUP] Attempt to override undefined parameter
/home/rady/caravel/openframe/caravel_openframe_user_project//verilog/rtl/picosoc.v, 736
Attempting to override undefined parameter "IFACE_ADR", will ignore it.

I'm not sure why this works with iverilog.
I fixed that at commit can you take a look?

How to chain the 2 timers?

I tried to add test for chaining the 2 timers but I can't figure out the right configuration for the registers.

Need the openframe_project_wrapper.gds on the main branch

This gds is needed for precheck defaults check

changing spi master mode gives wrong value

When changing the spi master mode from 0 to 1 the written data at sdo is faster 1 cycle the the sck.
Here is a waveform of writing 0x1 when mode is 1(reading at negative edge )

This is read as 0x3

The waveform when writing 0x1 when mode is 0 (reading at posedge)

Hold violation on path with start point `gpio_in[38]` (clock)

Startpoint: gpio_in[38] (clock source 'clk')
Endpoint: _32086_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Corner: Typical

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clk (rise edge)
                          0.00    0.00   clock source latency
                  1.00    0.00    0.00 ^ gpio_in[38] (in)
     1    0.14                           gpio_in[38] (net)
                  1.11    0.05    0.05 ^ clkbuf_0_gpio_in[38]/A (sky130_fd_sc_hd__clkbuf_16)
                  0.13    0.35    0.40 ^ clkbuf_0_gpio_in[38]/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.10                           clknet_0_gpio_in[38] (net)
                  0.13    0.01    0.41 ^ clkbuf_1_0__f_gpio_in[38]/A (sky130_fd_sc_hd__clkbuf_16)
                  0.16    0.23    0.64 ^ clkbuf_1_0__f_gpio_in[38]/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.15                           clknet_1_0__leaf_gpio_in[38] (net)
                  0.16    0.01    0.65 ^ _26519_/B2 (sky130_fd_sc_hd__a22o_2)
                  0.03    0.14    0.79 ^ _26519_/X (sky130_fd_sc_hd__a22o_2)
     1    0.00                           _02974_ (net)
                  0.03    0.00    0.79 ^ _32086_/D (sky130_fd_sc_hd__dfxtp_1)
                                  0.79   data arrival time

                          0.00    0.00   clock clk (rise edge)
                          0.00    0.00   clock source latency
                  1.19    0.00    0.00 ^ gpio_in[38] (in)
     1    0.14                           gpio_in[38] (net)
                  1.30    0.06    0.06 ^ clkbuf_0_gpio_in[38]/A (sky130_fd_sc_hd__clkbuf_16)
                  0.14    0.41    0.47 ^ clkbuf_0_gpio_in[38]/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.10                           clknet_0_gpio_in[38] (net)
                  0.14    0.01    0.48 ^ clkbuf_1_0__f_gpio_in[38]/A (sky130_fd_sc_hd__clkbuf_16)
                  0.16    0.25    0.73 ^ clkbuf_1_0__f_gpio_in[38]/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.15                           clknet_1_0__leaf_gpio_in[38] (net)
                  0.18    0.04    0.77 ^ _15485_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.05    0.17    0.94 ^ _15485_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _05023_ (net)
                  0.05    0.00    0.94 ^ _15486_/B (sky130_fd_sc_hd__and2b_2)
                  0.36    0.39    1.32 ^ _15486_/X (sky130_fd_sc_hd__and2b_2)
     2    0.07                           _05024_ (net)
                  0.36    0.02    1.34 ^ clkbuf_0__05024_/A (sky130_fd_sc_hd__clkbuf_16)
                  0.10    0.27    1.61 ^ clkbuf_0__05024_/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.07                           clknet_0__05024_ (net)
                  0.10    0.01    1.62 ^ clkbuf_1_0__f__05024_/A (sky130_fd_sc_hd__clkbuf_16)
                  0.19    0.26    1.88 ^ clkbuf_1_0__f__05024_/X (sky130_fd_sc_hd__clkbuf_16)
    18    0.18                           clknet_1_0__leaf__05024_ (net)
                  0.19    0.01    1.89 ^ _15487_/B1 (sky130_fd_sc_hd__a21oi_2)
                  0.30    0.30    2.19 v _15487_/Y (sky130_fd_sc_hd__a21oi_2)
     2    0.14                           _00144_ (net)
                  0.30    0.02    2.21 v clkbuf_0__00144_/A (sky130_fd_sc_hd__clkbuf_16)
                  0.09    0.33    2.54 v clkbuf_0__00144_/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.11                           clknet_0__00144_ (net)
                  0.09    0.00    2.54 v clkbuf_1_0_0__00144_/A (sky130_fd_sc_hd__clkbuf_8)
                  0.11    0.23    2.77 v clkbuf_1_0_0__00144_/X (sky130_fd_sc_hd__clkbuf_8)
     4    0.10                           clknet_1_0_0__00144_ (net)
                  0.11    0.00    2.78 v clkbuf_2_0_0__00144_/A (sky130_fd_sc_hd__clkbuf_8)
                  0.14    0.25    3.03 v clkbuf_2_0_0__00144_/X (sky130_fd_sc_hd__clkbuf_8)
     4    0.13                           clknet_2_0_0__00144_ (net)
                  0.16    0.04    3.07 v clkbuf_3_0_0__00144_/A (sky130_fd_sc_hd__clkbuf_8)
                  0.11    0.26    3.33 v clkbuf_3_0_0__00144_/X (sky130_fd_sc_hd__clkbuf_8)
     8    0.09                           clknet_3_0_0__00144_ (net)
                  0.11    0.01    3.34 v clkbuf_5_0_0__00144_/A (sky130_fd_sc_hd__clkbuf_8)
                  0.05    0.20    3.53 v clkbuf_5_0_0__00144_/X (sky130_fd_sc_hd__clkbuf_8)
     4    0.03                           clknet_5_0_0__00144_ (net)
                  0.05    0.00    3.54 v clkbuf_6_0__f__00144_/A (sky130_fd_sc_hd__clkbuf_16)
                  0.12    0.24    3.78 v clkbuf_6_0__f__00144_/X (sky130_fd_sc_hd__clkbuf_16)
    26    0.18                           clknet_6_0__leaf__00144_ (net)
                  0.12    0.01    3.78 v clkbuf_leaf_795__00144_/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.20    3.99 v clkbuf_leaf_795__00144_/X (sky130_fd_sc_hd__clkbuf_16)
     6    0.04                           clknet_leaf_795__00144_ (net)
                  0.05    0.00    3.99 v _1636_1645/A (sky130_fd_sc_hd__inv_2)
                  0.02    0.04    4.03 ^ _1636_1645/Y (sky130_fd_sc_hd__inv_2)
     1    0.00                           net5674 (net)
                  0.02    0.00    4.03 ^ _32086_/CLK (sky130_fd_sc_hd__dfxtp_1)
                          0.10    4.13   clock uncertainty
                          0.00    4.13   clock reconvergence pessimism
                         -0.03    4.10   library hold time
                                  4.10   data required time
-----------------------------------------------------------------------------
                                  4.10   data required time
                                 -0.79   data arrival time
-----------------------------------------------------------------------------
                                 -3.30   slack (VIOLATED)

The reason for opening this issue is that the start point and the clock triggering this path have the same source gpio_in[38] (clk) which is a bit odd. This only appeared after #5

Need reset synchronization

The openframe project fails one testbench where the CPU fails to start up after bringing the chip out of SPI reset. Both the RESETB pin and the SPI reset need to be synchronized to the core clock.

Since the housekeeping SPI resets only on the POR signal, then there is no problem simply synchronizing the core reset to the core clock. The implementation should allow the reset to be set at any time, but the reset should only be released in synchronization with the clock (on the falling edge, to give a clock half-cycle time between reset release and the next clock positive edge).

The implementation should be: all_resetb = (RESETB pin & SPI resetb) ; core_resetb = (all_resetb & all_resetb_sync) where all_resetb_sync is all_resetb passed through two flops clocked by the inverse of the core clock, and reset to zero on porb.

RTL changes needed for iverilog v12

In the latest release of Iverilog, version 12.0.0, a new error has been introduced that detects mixing between old and new declaration module styles within RTL code. like the declaration here the compile resulted in the following error:

/home/rady/caravel/openframe/caravel_openframe_project//verilog/rtl/simple_spi_master.v:187: error: 'err_out' has already been declared in this scope.

Explanation of the issue is well defined in this comment by dave_59.

I will add the required RTL need.

GPIO vector [0] and [43] input are shorted with the output

The input to vector_gpio_in[21:20] are connected to vector_gpio_out rather than the external GPIOs.
Is this intended ?
@RTimothyEdwards can you please take a look ?
https://github.com/RTimothyEdwards/caravel_openframe_project/blob/main/verilog/rtl/picosoc.v#L653

rtimothyedwards / caravel_openframe_project Goto Github PK

caravel_openframe_project's Issues

master spi interrupt behaviour

counter interrupts

Missing pins in template def

Needs multiple power supply connections

Wrong dimensions for `gpio_analog_pol[33]` in template def

Select out of bounds on signal `gpio_dat_o[*]`

Housekeeping reset register doesn't function

Flashing isn't working with vcs

How to chain the 2 timers?

Need the openframe_project_wrapper.gds on the main branch

changing spi master mode gives wrong value

Hold violation on path with start point `gpio_in[38]` (clock)

Need reset synchronization

RTL changes needed for iverilog v12

GPIO vector [0] and [43] input are shorted with the output

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