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cbc

CBC block cipher mode of operation for AES.

ccm

ccm mode hardware implementation

chacha

Verilog 2001 implementation of the ChaCha stream cipher.

chacha20-poly1305

Hardware implementation of the ChaCha20-Poly1305 AEAD construction

chacha_testvectors

Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.

chaskey

Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.

cmac

Implementation of the CMAC keyed hash function using AES as block cipher.

coretest

Test structure for cores developed as part of the Cryptech Open HSM project

coretest_bp_entropy

Coretest system for testing the FPGA based entropy source by Berndt Paysan.

coretest_fpga_entropy

Coretest system for testing FPGA based entropy source.

coretest_hashes

The coretest system combined with cryptographic hash functions.

coretest_test_core

The coretest module combined with the test_core as a test module.

cryptopals

Personal repo for working on the Cryptopals challenges.

curve25519

Verilog 2001 of the Curve25519 elliptic curve based function.

demoparts

Repo for assorted demoparts

dilithium

Fork for testing of porting to R5

ed25519

ed25519 public key signature implemented in Verilog.

ed25519-unsafe-libs

List of unsafe ed25519 signature libs

ent_random_sequence_tester

Utility for testing random and pseudorandom sequences, either as bytes or bit streams, reporting entropy, mean value, serial correlation, chi square, and Monte Carlo estimate of an value, serial correlation, chi square, and Monte Carlo estimate of π.

espresso-logic

A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.

extract_ev_data

Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.

figaro

Implementation of the FiGaRO TRNG for FPGAs

fltbwt

Burrows-Wheeler Transform tool including decoder in 6502 assembler.

fltfpga

FairLight FPGA demo board based on TerasIC G5C

fltintro

New intro design for FairLight. Hopefully done before DS 2017.

fpga_entropy

Test implementation of FPGA-internal entropy source.

fpga_eth_filter

FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Card

fpga_ntp_server

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

gcm

Galois Couter Mode implementation in Verilog.