Joachim Strömbergson's Projects
CBC block cipher mode of operation for AES.
ccm mode hardware implementation
Verilog 2001 implementation of the ChaCha stream cipher.
Hardware implementation of the ChaCha20-Poly1305 AEAD construction
Generator and Internet Draft (I-D) documenting test vectors for the stream cipher ChaCha.
Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.
Implementation of the CMAC keyed hash function using AES as block cipher.
Test structure for cores developed as part of the Cryptech Open HSM project
Coretest system for testing the FPGA based entropy source by Berndt Paysan.
Coretest system for testing FPGA based entropy source.
The coretest system combined with cryptographic hash functions.
The coretest module combined with the test_core as a test module.
Personal repo for working on the Cryptopals challenges.
Verilog 2001 of the Curve25519 elliptic curve based function.
Repo for assorted demoparts
Fork for testing of porting to R5
ed25519 public key signature implemented in Verilog.
List of unsafe ed25519 signature libs
Utility for testing random and pseudorandom sequences, either as bytes or bit streams, reporting entropy, mean value, serial correlation, chi square, and Monte Carlo estimate of an value, serial correlation, chi square, and Monte Carlo estimate of π.
A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.
Pure Python program used to extract EV data from Mozilla CA roots. Used to generate EV validation data in sslyze.
Implementation of the FiGaRO TRNG for FPGAs
Burrows-Wheeler Transform tool including decoder in 6502 assembler.
FairLight FPGA demo board based on TerasIC G5C
New intro design for FairLight. Hopefully done before DS 2017.
Test implementation of FPGA-internal entropy source.
FPGA based Ethernet traffic filter and manipulator for the TerasIC ETHERNET-HSMC Card
Package manager and build abstraction tool for FPGA/ASIC development
Galois Couter Mode implementation in Verilog.