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fpga_workshop_collaterals

Input files and commands needed for the workshop, sorted daywise

frigate

NVR with realtime local object detection for IP cameras

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

gf_cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

implementation-of-error-detection-codes-in-python

implementation-of-line-encoding-schemes-in-python

infiresv0.1-rv32ic-core

"Infires" is a series of RISC-V Cores developed using TL-Verilog. Infiresv0.1.x consists of different pipelined variants RV32I/C Cores.

lacpo

Learning-based Architecture-level CPU Power modeling

mltk

A Python package with command-line utilities and scripts to aid the development of machine learning models for Silicon Lab's embedded platforms

multisim-simulations-and-spice-files-analog-electronic-circuits

This is my collection of Multisim Simulations for the classic analog electronic circuits ranging from rectifiers, oscillators, voltage regulators , Astable, Bistable , Monostable Multivibrators.

myth-rv32i-core-akilm

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

my_edalize

Edalize - WIP support for additional tools and flows

openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

openlane_build_script

This script builds openlane and all its dependencies on an Ubuntu (only) System.

openroad-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

physical-design-with-openlane-using-sky130-pdk

This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified

pkg_cv_ros_tutorial_by_dhanuzch

This is the repo consisting of the ROS package used in "Using OpenCV with Gazebo in ROS" tutorial series by @dhanuzch

qemu_systemc_app

Sample ARM application for QEMU/SystemC-based HW/SW Co-Simulation

qunetsim

A quantum network simulation framework.

retrieval-based-voice-conversion-webui

Voice data <= 10 mins can also be used to train a good VC model!

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v_myth_workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop

riscv_myth_fpga

For use in RedwoodEDA's MYTH course

rphax

RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and create a Zynq based block design.

rtl-design-using-verilog-with-sky130-technology

This repository has a quick documentation covering the basics of RTL Design using verilog using the open source Skywater 130nm PDK. This covers the basics of RTL Design using Verilog and simulation, Logic synthesis and optimisations

sandpiper_test

Testing SandPiper_1.9-2018_02_11-beta_distro

sauria

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

sdes_web

sequential-binary-multiplier---design-and-synthesis-with-skywater-pdk

This repository highlights the design procedure of a simple sequential binary multiplier manually using ASMD Charts and its RTL implementation in verilog and synthesis using Skywater130nm pdk. Refer Concept.pdf to look at the design steps

serv

SERV - The SErial RISC-V CPU