shariethernet,Shrihari G,github

Hi there 👋

Driven by my zeal for Silicon Design, I am primarily an RTL Design Engineer who can cross boundaries from Micro-architecture definition to architectural modeling as well as perform formal verification. My research interests are in the fields of Heterogeneous Architectures, Machine Learning Accelerators, Power optimization algorithms, and System Level Modelling. I also work on TL-Verilog, an emerging High-Level HDL, and its ecosystem. I look forward to creating a valid imprint on innovation, trying to address unsolved challenges in silicon engineering

I work on Hardware Accelerators, Co-processor interconnect fabrics, RISC-V based Cores, and Low Power Microarchitecures
I contribute towards @RedwoodEDA's TL-Verilog ecosystem by developing EDA Tools, EDA-CAD Flows, TL-Verilog based designs, FPGA Labs etc.,
Connect with me on Linkedin, Email, have a look at my website or resume here

Shrihari G's Projects

siliconcompiler

A modular build system for hardware

siliconcompiler_sandpiper_saas_example

Example of using SiliconCompiler with Sandpiper-SaaS as the Frontend

tiny_yolov3_face_mask_detect

Real-time tiny-YOLOv3 face mask detection on Ultra96v2

tlv_lib

General-purpose TL-Verilog libraries.

virtual-fpga-lab

This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.

vitis-ai

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.