Driven by my zeal for Silicon Design, I am primarily an RTL Design Engineer who can cross boundaries from Micro-architecture definition to architectural modeling as well as perform formal verification. My research interests are in the fields of Heterogeneous Architectures, Machine Learning Accelerators, Power optimization algorithms, and System Level Modelling. I also work on TL-Verilog, an emerging High-Level HDL, and its ecosystem. I look forward to creating a valid imprint on innovation, trying to address unsolved challenges in silicon engineering
- I work on Hardware Accelerators, Co-processor interconnect fabrics, RISC-V based Cores, and Low Power Microarchitecures
- I contribute towards @RedwoodEDA's TL-Verilog ecosystem by developing EDA Tools, EDA-CAD Flows, TL-Verilog based designs, FPGA Labs etc.,
- Connect with me on Linkedin, Email, have a look at my website or resume here