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Name: Shrihari G

Type: User

Location: United States

Hi there 👋

Driven by my zeal for Silicon Design, I am primarily an RTL Design Engineer who can cross boundaries from Micro-architecture definition to architectural modeling as well as perform formal verification. My research interests are in the fields of Heterogeneous Architectures, Machine Learning Accelerators, Power optimization algorithms, and System Level Modelling. I also work on TL-Verilog, an emerging High-Level HDL, and its ecosystem. I look forward to creating a valid imprint on innovation, trying to address unsolved challenges in silicon engineering

I work on Hardware Accelerators, Co-processor interconnect fabrics, RISC-V based Cores, and Low Power Microarchitecures
I contribute towards @RedwoodEDA's TL-Verilog ecosystem by developing EDA Tools, EDA-CAD Flows, TL-Verilog based designs, FPGA Labs etc.,
Connect with me on Linkedin, Email, have a look at my website or resume here

Shrihari G's Projects

1st-claas

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

accelerating_standard_and_modified_aes128

advanced-physical-design-using-openlane-sky130-overview

aes128

Implementation of AES-128 bit key algorithm in TL-Verilog

aes_adl2_fpga

algebraic-nnhw

AI and matrix multiplication accelerator architectures requiring half the multipliers

approximate-dadda-multipliers

asciiquarium

Enjoy the mysteries of the sea from the safety of your own terminal!

bdw

BSC Development Workstation (BDW)

caffe

Caffe: a fast open framework for deep learning.

cgra-me

This repository contains CGRA-ME Framework from University of Toronto. This is uploaded in this repository only for quick and easy access.

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

cim_test_harness

cnnmlp_profiling

controlpath-datapath-asmd-designtosynthesiswithskywater130

This repository highlghts the manual design of datapath and control path with ASMD Chart and its comparison with the synthesis from behavior level RTL and finally the synthesised design is mapped to the Skywater130nm standard cells and Netlist is generated

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

cplusplus20fundamentalslivelessons

Source code examples for our **C++20 Fundamentals LiveLessons** Videos

cpu_fpga

Implement all instructions for RISC-V including Branch instructions. This repository will provide the automation flow for running the design into hardware.

custom_zynq_1

AXI4 Lite Slave - Zynq based Design

darknet2caffe

Convert darknet weights to caffemodel

darknet_ab

YOLOv4 / Scaled-YOLOv4 / YOLO - Neural Networks for Object Detection (Windows and Linux version of Darknet )

dhanuzch

Profile README

dnndk-yolov3

"Forked" from Xilinx/Edge-AI-Platform-Tutorials

edalize_18_6

An abstraction library for interfacing EDA tools

edalize_sandpiper_example

Example for using sandpiper with edalize front-end

esp8266_deauther

Scan for WiFi devices, block selected connections, create dozens of networks and confuse WiFi scanners!

flight-controller-design-for-shakthi-c64-processor

This is a SIMULINK based Control System Design for a Quadcopter. The Control System was designed in SIMULINK and the Embedded C Code and Verilog code were generated using SIMULINK Coder. This was aimed at developing a flight controller using the RISCV ISA based SHAKTHI-C64-Vajra Microprocessor developed at RISE Labs, IIT Madras, India

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