1. Barrel jack should be locking package to help with selective soldering

2. Please nudge slide switch over to the left 5-10 mil, just to help avoid depanelization damage on that part.

3. Add board and standoff dimensions. possibly connector center lines?

4. Can we fit the complete board name in the silk? Maybe if "explorer" is slightly smaller.

5. space jumpers out for more standard labeling

6. add bottom silk for xbee breakout headers

7. Left side header silk should be aligned to the right side of each text object is evening spaced away from headers

Just realized, if we want to test post SS, then we'll need test points on the following nets:

RS232-RTS
RS232-CTS
RS232-DTR
RS232-RX
RS232-TX
N$15 (aka the "raw" power input)

Sorry for the last minute issue. I didn't initially think we would test post SS, but I now I realize it makes more sense than having to break the normal assembly flow.

1. Some nets are thicker than 0.006

2. C3, C5, C6 have right angles off the pin, they need at least one grid space drawn straight out from pin

3. "v1.3" shouldn't have the "dot"

4. 2 unnecessary GND text labels and 1 unnecessary 3.3V text label of nets off of JP2

5. add VCC input range to schematic

6. the azy slide switch has a "$" in it's name

7. the rs232 connector prefix should be a "JP" not an "X"

8. Update momentary reset switch to the newest device in our library. the newest one has only two pins

9. Not all components have proper PROD_IDs

10. LED names sould be simply an "L#"

11. Barrel Jack prefix should be JP not just J, also the package is missing the >NAME text object