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100-days-of-rtl

100-days-of-rtl-code

100-days-of-rtl1

100-days-of-rtl2

100-days-off-rtl

100-days-ofrtl

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

100daysofrtl

100 Days of RTL

100daysofrtl0

100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves committing to working on RTL based digital designs for 100 consecutive days. The goal is to build a solid foundation of knowledge and experience in the field.

100daysofrtll

I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.

100daysofrtlll

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

2-way-set-associative-cache-controller

Synthesizable and Parameterized Cache Controller in Verilog

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754

6502

Verilog implementation of a MOS6502 compatible CPU core.

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

adder

implementation and test bench using System Verilog

advance-fpga-design

Examples discussed in the book: "Advanced FPGA design: Architecture, Implementation, and Optimization" by Steve Kilts, in System Verilog.

aead_aes_siv_cmac

Hardware implementation of the AEAD_AES_SIV_CMAC

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes_6502

My attempt at making a fast AES-128 implementation on MOS 6502

aes_mask

Experimental core for performing masking of AES by generating noise.

ahb_sram

alu-8bit

Use a 8-bit full-adder/subtractor to create a 8-bit ALU .

alu_design_verification_uvm

implementation and test bench using UVM

amba_axi_ahb_apb

AMBA bus lecture material

apb-protocol

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

ascon

Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm

avalanche_entropy

Entropy collector and provider for an external avalanche noise based entropy source.

awesome-fpga-list

A collection of some awesome public FPGA projects.

axi-sdcard-high-speed-controller

A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)