WELCOME TO MY 100DAYSOFRTL
My Name is Ummidi Chandrika, I mostly use Xilinx ISE 14.7 Design Suite and sometimes Modelsim software for the simulation of RTL Codes. And The Synthesis is performed by using Intel Quartus Prime Software.
Here is the list of Day wise RTL Codes:
Day 1 : Clock Divider
Day 2 : Johnson Counter
Day 3: Ring Counter
Day 4: 5 Input Majority Circuit
Day 5: Parity Generator
Day 6: Binary to One Hot Encoder
Day 7: 4-bit BCD Synchronous Counter
Day 8: 4-bit Carry LookAhead Adder
Day 9: N-bit Comparator
Day 10: Serial in Serial Out Shift Register
Day 11: Serial in Parallel Out Shift Register
Day 12: Parallel in Parallel Out Register
Day 13: Parallel In Serial Out Register
Day 14: Bidirection Shift Register
Day 15: PRBS Sequence Generator
Day 16: 8-Bit Subtractor
Day 17: 8-Bit Adder/Subtractor
Day 18: 4-bit Multiplier
Day 19: Fixed Point Division
Day 20: Master Slave JK Flip Flop
Day 21: Positive Edge Detector
Day 22: BCD adder
Day 23: 4-bit Carry Select Adder
Day 24: Moore FSM 1010 Sequence detector
Day 25: N:1 Mux
Day 26: BCD TimeCount
Day 27: 3-1 Mux
Day 28: BCD to Seven Segment Display
Day 29: D Latch using 2:1 MUX
Day 30: 8-Bit Barrel Shifter
Day 31: 1-bit Comparator using 4X1 Mux
Day 32: Logical, Algebraic, and Rotate Shift Operations
Day 33: ALU
Day 34: 4-Bit Asynchronous Down Counter
Day 35: Mod-N UpDown Counter
Day 36: Universal Binary Counter
Day 37: Universal Shift Register
Day 38: CN( Change-No change Flipflop) using 2:1 Mux
Day 39: Frequency divider by odd Numbers
Day 40: Greatest Common Divisor using Behavioural Modelling
Day 41: Greatest Common Divisor via FSM
Day 42: Single Port RAM
Day 43: Dual Port RAM
Day 44: Clock Buffer
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