VHDL exporter about peakrdl-regblock HOT 4 OPEN

Thanks for the enthusiasm!
At this moment, I don't have any immediate plans to add support for a VHDL exporter. Ever since I switched to the "dark side" and started using SystemVerilog exclusively, VHDL has fallen out of favor in my projects.

That said, I agree that it would be valuable to have an option to generate VHDL. As far as I can tell, nearly all of the language concepts I use in the SystemVerilog exporter could technically be transcribed to VHDL, so it is certainly doable (with the exception of SV interface ports. We'll have to wait for VHDL 2019 to be more widely adopted in tools).
So in short, its not on my current roadmap, but I also don't want to rule it out, since it could make for an interesting enhancement in the future.

I'll keep this feature request open in case I feel inspired to add this 😄

from peakrdl-regblock.

Thanks for pointing me to this!
I have reached out to the DesyRDL folks and see if they are interested in having their tool be a plugin to the PeakRDL command line application I released recently.

I'll leave this issue open in case I decide to extend support to VHDL in the future.

from peakrdl-regblock.

Just a quick update. It appears that hectare has many drawbacks and produces wrongly synthesisable code, but I've found a way better alternative (and a successor to hectare): https://gitlab.desy.de/fpgafw/tools/desyrdl.

It looks nice in terms of supported features and quality of generated code and most importantly is actively maintained. It also uses VHDL records, similar to this project, so the regfile interfacing works nicely. I recommend it to anyone looking for a VHDL generator.

Actually, I wonder if this issue could be closed as DesyRDL looks really good in terms of quality. What do you think @amykyta3?

from peakrdl-regblock.

Sure, sounds good 👍

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