32 bit cpu model designed in VHDL
This project was part of my dissertation for my Electrical and Computer Engineering Degree. The model is pure RTL except from the clock generator and the ram. The DP32 is a simple cpu for educational purposes and has a minimal set of instructions. In the code there is a sample programe loaded in ram. To test the model you will need a VHDL simulator
At the moment there is no documentation and the code is a single file. I plan to separate the files and some docs.
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