why the firmware speed will be lower if i make all config space from .coe file? about pcileech-fpga HOT 9 CLOSED

@xingkong158 what software is that?

telescan

from pcileech-fpga.

Hi,

How does the config space when doing lspci -d 10ee:0666 -xxxx (in Linux as root) look like on your modified device as compared to the correct one you're trying to clone? (replace 10ee:0666 here with whatever vendor/device id you're using).

Chances are that you're either looking at a very basic legacy device or that there are some errors in the config. Some computers disallow reads using the "normal" algorithm with 4kB read / PCIe tag on old legacy hardware or when there is some errors (I think related to capabilities, but I'm not completely sure).

from pcileech-fpga.

from pcileech-fpga.

Hi, I don't see the image you're trying to show. But if you do lspci -tv you'll see all the devices and their device ids in a tree structure (or you may have to do lspci -n for that I don't remember.

from pcileech-fpga.

brother this one, and i want to know where can custom all configuration space header?

from pcileech-fpga.

@xingkong158 what software is that?

from pcileech-fpga.

@xingkong158 You may try to edit the pcie xci file before generating the core. If this setting is unavailable to customize to its fullest extent there I know others what have then edited the auto-generated verilog files that Vivado generates for the PCIe core.

from pcileech-fpga.

i want to change it to same, but if i change here

i cant get currect value.

the picture currect value = Captured Slot Power Limit Value 01001011, 01001011 ="4B". but i change "SLOT_CAP_SLOT_POWER_LIMIT_VALUE" to 4B, i still cant get right value with my firmware.

from pcileech-fpga.

Hi,

Editing the core manually is not something I'm experienced in and I'd be of very limited help asking questions about that. I just haven't looked into it at the detail level you require :\

But,

There is something called DRP, which is a debug port that allows you from software to set some of the internal workings of the core before it's brought online.

I haven't tested this, but you can try to replace the 4 lines of 64'h00000000_00000000, here with:

            64'h00000000_00000000,
            64'h5100ffff_801c2377,  // DRP ADDR: SLOT_CAP_SLOT_POWER_LIMIT_SCALE/VALUE
            64'h120cffff_801a2377,  // DRP DATA: LIMIT_SCALE=0,LIMIT_VALUE=4B,SSL_MESSAGE_AUTO=0
            64'h20002000_80022377,  // DRP WRITE EN

to write to the DRP debug port before the PCIe core is brought online. Maybe this will help (or maybe not).

More information about the DRP interface is found in the Xilinx PCIe core guide / data sheet.

Also, you may edit the file pcie_7x_0.xci before generating the core. I suspect you've already tried this though and that it didn't work.

Please let me know how it goes with using the DRP debug port, and best wishes.

from pcileech-fpga.