ultraembedded / core_ddr3_controller Goto Github PK

Why in the top.v, you made ddr3_reset_n = 1'b0 ddr3_cs_n = 1'b1,rather than let ddr3_reset_n and ddr3_cs_n be the outport of phy?

Hi,

I would like to ask how I could use your core with Microblaze in block design?

Thank you for your help!

Did someone actually manage to implement this design?

Simple AXI instructions that work with Xilinx MIG dont work here at all. Like bvalid never goes high. Or you want to read from DDR? Have fun waiting for arready. Whats up with that? How was the core tested? There is no detail about it