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Verilog to Routing -- Open Source CAD Flow for FPGA Research

Home Page: https://verilogtorouting.org

License: Other

Makefile 0.40% Verilog 34.60% Python 4.02% Shell 0.78% Perl 0.32% C 1.74% C++ 56.07% Yacc 0.64% Lex 0.21% JavaScript 0.23% CSS 0.01% HTML 0.07% CMake 0.03% Dockerfile 0.01% Cap'n Proto 0.02% Nix 0.01% Tcl 0.09% Ruby 0.01% TeX 0.46% SystemVerilog 0.29%
vtr fpga cad verilog placement routing synthesis eda vpr

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