A link is given in the quick start session in README.md which requires users to download the vitis-ai-docker-runtime image. The link is not accessible, returning a 404 page.

hi,
I have configured the docker-based model quantization tool (CPU version). However, I encountered the following problems when I use the Vitis AI Compiler tools.
The commond 'vai_c_tensorflow' need a parameter --arch arch.json. But for zynq 7010，where can I get the arch.json ? Or is there any document for edit it ?

WARNING: Logging before InitGoogleLogging() is written to STDERR
F1229 23:15:57.683681 4001 elf2xir.hpp:317] Check failed: kernel_subgraphs.size() == 2 (0 vs. 2) only support one input kernel and one dpu kernel.
*** Check failure stack trace: ***
Aborted

When i do "sh 1_caffe_quantize.sh",it's return that.

0306 01:41:38.437182 396 layer_factory.hpp:123] Creating layer data
I0306 01:41:38.437286 396 net.cpp:140] Creating Layer data
I0306 01:41:38.437325 396 net.cpp:455] data -> data
I0306 01:41:38.437364 396 net.cpp:455] data -> label
I0306 01:41:38.437518 396 image_data_layer.cpp:87] Opening file /home/xxx/fix_models_hrr_classification/val.txt
I0306 01:41:38.437568 396 image_data_layer.cpp:97] Shuffling data
I0306 01:41:38.437577 396 image_data_layer.cpp:102] A total of 0 images.
Segmentation fault (core dumped)

There are a few questions below.

1. Is the picture placed under path a xxxx/vitis-ai-tools-examples/images?
2. Must the name of the image begin with "ILSVRC2012_xxx"?

500 images in the images folder.
Where is the problem？

When I start the xilinx/vitis-ai:tools-1.0.0-cpu container, bash reports three errors:

sysadmin@ml0:~/devel/xilinx/Vitis-AI$ ./docker_run.sh xilinx/vitis-ai:tools-1.0.0-cpu
Unable to find image 'xilinx/vitis-ai:tools-1.0.0-cpu' locally
tools-1.0.0-cpu: Pulling from xilinx/vitis-ai
...
bash: export: `1': not a valid identifier
bash: export: `14:51:32': not a valid identifier
bash: export: `2019': not a valid identifier

==========================================
__      ___ _   _                   _____ 
\ \    / (_) | (_)            /\   |_   _|
 \ \  / / _| |_ _ ___ ______ /  \    | |  
  \ \/ / | | __| / __|______/ /\ \   | |  
   \  /  | | |_| \__ \     / ____ \ _| |_ 
    \/   |_|\__|_|___/    /_/    \_\_____|

==========================================

Docker Image Version: 1.0.0
Build Date: Sun
VAI_ROOT=/opt/vitis_ai
For TensorFlow Workflows do:
  conda activate vitis-ai-tensorflow
For Caffe Workflows do:
  conda activate vitis-ai-caffe
sysadmin@ml0:/workspace$

Can this issue prevent the container from working properly?

Hi,
I failed to import the vai library with the CPU container : xdock:5000/vitis-ai 1.0.0-cpu .

from vai.dpuv1.tools.compile.bin.xfdnn_compiler_caffe import CaffeFrontend as xfdnnCompiler
Traceback (most recent call last):
File "", line 1, in
ModuleNotFoundError: No module named 'vai'

Following is the $PYTHONPATH information:

/workspace/alveo/overlaybins/setup.sh

Using VAI_ALVEO_ROOT

/workspace/alveo

Using LD_LIBRARY_PATH

/opt/xilinx/xrt/lib:

Using LIBXDNN_PATH

/lib/libxfdnn.so

PYTHONPATH

/workspace/alveo:/workspace/alveo/apps/yolo:/workspace/alveo/apps/yolo/nms:/workspace/alveo/xfmlp/python:/opt/xilinx/xrt/python:/workspace/alveo:/workspace/alveo/apps/yolo:/workspace/alveo/apps/yolo/nms:/workspace/alveo/xfmlp/python:/opt/vitis_ai/compiler

Verifying XILINX_XRT

XILINX_XRT : /opt/xilinx/xrt
PATH : /opt/xilinx/xrt/bin:/opt/xilinx/xrt/bin:/opt/vitis_ai/conda/bin:/opt/vitis_ai/utility:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
LD_LIBRARY_PATH : /opt/xilinx/xrt/lib:/opt/xilinx/xrt/lib:
PYTHONPATH : /opt/xilinx/xrt/python:/workspace/alveo:/workspace/alveo/apps/yolo:/workspace/alveo/apps/yolo/nms:/workspace/alveo/xfmlp/python:/opt/xilinx/xrt/python:/workspace/alveo:/workspace/alveo/apps/yolo:/workspace/alveo/apps/yolo/nms:/workspace/alveo/xfmlp/python:/opt/vitis_ai/compiler

Thanks,
Bean

When I use vitis-ai-caffe to compile my caffe model .
I got a err like:
"[VAI_C][Warning]Only 'SUM' type is supported for Eltwise,current layer is [stem_activation]"
"[VAI_C][Warning]Only 'SUM' type is supported for Eltwise,current layer is [block1a_activation]"
"[VAI_C][Error]unrecognized Caffe layer type [Reshape]"
"[VAI_C][Error]Parsing layer graph failed"
it looks like DPU does not support Reshape and Eltwise layer(except 'SUM'),but it difficults to change "Reshape" layer in my caffe model.
Is there some suggestions for me to avoid this error?
Thanks!

@wilderfield
Clarification needed (can be applicable to Alveo cards)
this given libraries are only applicable to zu102,zu104 boards? https://github.com/Xilinx/Vitis-AI/tree/master/Vitis-AI-Library

The markdown document: https://github.com/Xilinx/Vitis-AI/blob/master/DPU-TRD/prj/Vitis/README.md

This doc references UG1360 in section 5.4 which doesn't seem to exist right now. Am I missing something?

build adas_detection meet cannot find -lhineon/ln2cube error, compile the model on the board directly

module path: Vitis-AI/mpsoc/vitis_ai_samples_zcu104/adas_detection

error info:
/usr/lib/gcc/aarch64-xilinx-linux/8.2.0/../../../../aarch64-xilinx-linux/bin/ld: cannot find -lhineon
/usr/lib/gcc/aarch64-xilinx-linux/8.2.0/../../../../aarch64-xilinx-linux/bin/ld: cannot find -ln2cube

whatever face detect given in apps folder here was supported by ml-suite only not updated

Downloading the GPU tools container gives a bad and very small download. When I navigate in a browser to the link I get a 404 message from the Xilinx website.

U280 is not listed in the supported card from this repo or from user guide (https://www.xilinx.com/support/documentation/sw_manuals/vitis_ai/1_0/ug1414-vitis-ai.pdf). How U280 is supported? It should, but not tested? If you can tell steps of adding U280 support, we can give a try and bring a PR for review.

We have a ES version of U280, hope this is ok.

Thank you

When I try to run script 6_tf_compile.sh from Vitis-AI/mpsoc/vitis-ai-tool-example/ (with conda environment vitis-ai-tensorflow) the following problem occurs:

**************************************************
* VITIS_AI Compilation - Xilinx Inc.
**************************************************
/opt/vitis_ai/compiler/arch/dpuv2/ZCU104/ZCU104.json
Traceback (most recent call last):
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/vai_c_tensorflow", line 154, in <module>
    compiler = VAI_TensorFlow_Frontend(args)
  File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/vai_c_tensorflow", line 101, in __init__
    from dnnc.dnnc_compiler_interface import DNNCFrontend
ModuleNotFoundError: No module named 'dnnc'

I am using docker image xilinx/vitis-ai:tools-1.0.0-cpu.

Hello,

I have a zcu 104 and I try to start examples as it is explain here :

https://github.com/Xilinx/Vitis-AI/blob/master/mpsoc/runtime_docker.md

I flashed the sd card with this img : xilinx-zcu104-dpu-v2019.2.img.gz and Etcher

then I successfully installed xilinx_vai_board_package like it is described in Vitis user guide p26 :

https://www.xilinx.com/support/documentation/sw_manuals/vitis_ai/1_0/ug1414-vitis-ai.pdf#unique_34

I managed to cross-compile applications in runtime docker, I tried the following examples :

- from dnndk : 
    - resnet50
    - adas_detection
    - segmentation

- from dnndk : 
    - adas_detection
    - segmentation

For all of these examples I obtain a black screen and the the board freezes.

I tried standalone connection (Display port) and ssh.

I haven't any signals on HDMI tx.

By ssh a black pop up appears and the board freezes.

I tried to see kernel log but I see nothing suspicious.

Did miss something on the setup ?

Best regards,

Matthieu

Hi,

I am trying to install and run the vitis-ai-docker-tools following the instructions under "Getting Started". I was able to install docker and put my linux user in the group docker. However, there is an issue when I ran the command "./docker_run.sh xilinx/vitis-ai:tools-1.0.0-cpu". Error messages:

docker: unknown server OS: .
See 'docker run --help'.

Could anyone support with this issue? Thanks!

Regards,
Louis

test

Hi, @wilderfield @sumitn-xilinx
Generated xclbin for x+ml (preprossing resize operation) with L3 vision.
For running x+ml application, please provide more details regarding, how to integrate preprocessing and ml acceleraion.
pp_pipeline.so not found.

Hi, I failed to build dpu.xclbin of zcu102_base. I've already installed XRT and source the bash files before building the target. Here is the error message. Does anyone know how to solve this problem? Thank you in advance.

INFO: [v++ 60-1453] Command Line: vpl -t hw -f /home/qsun/app/Xilinx/Vitis/2019.2/platforms/zcu102_base/zcu102_base.xpfm --remote_ip_cache binary_container_1/ip_cache -s --output_dir /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int --log_dir /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/logs/link --report_dir /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/reports/link --config /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link --no-info --tlog_dir /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/.tlog/v++_link_dpu --iprepo /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_sfm_xrt_top_1_0 --iprepo /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_dpu_xrt_top_1_0 --messageDb /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/run_link/vpl.pb /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/run_link

****** vpl v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423] Target device: zcu102_base
INFO: [VPL 60-1032] Extracting hardware platform to /home/qsun/Compiler/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
[23:32:28] Run vpl: Step create_project: Started
[23:32:29] Run vpl: Step create_project: Failed
[23:32:29] Run vpl: FINISHED. Run Status: create_project ERROR
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [23:32:29] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 674.367 ; gain = 0.000 ; free physical = 4080 ; free virtual = 59475
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:70: recipe for target 'binary_container_1/dpu.xclbin' failed
make: *** [binary_container_1/dpu.xclbin] Error 1

https://github.com/Xilinx/Vitis-AI/tree/master/mpsoc

Vitis AI User Guide link is broken

#!/bin/sh
TF_NETWORK_PATH=tf_yolov3_voc_416_416_65.63G
vai_q_tensorflow quantize --input_frozen_graph tf_yolov3_voc_416_416_65.63G/float/yolov3_voc.pb --input_fn input_fn.calib_input --output_dir vai_q_output --input_nodes input_1 --output_nodes conv2d_59/BiasAdd,conv2d_67/BiasAdd,conv2d_75/BiasAdd --input_shapes ?,416,416,3 --calib_iter 50

alib_data/COCO_train2014_000000000036.jpg
10% (5 of 50) |##################### | Elapsed Time: 0:00:27 ETA: 0:04:07calib_data/COCO_train2014_000000000049.jpg
Traceback (most recent call last):
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1334, in _do_call
return fn(*args)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1319, in _run_fn
options, feed_dict, fetch_list, target_list, run_metadata)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1407, in _call_tf_sessionrun
run_metadata)
tensorflow.python.framework.errors_impl.InvalidArgumentError: output dimensions must be positive
[[{{node up_sampling2d_1/ResizeNearestNeighbor}} = ResizeNearestNeighbor[T=DT_FLOAT, align_corners=false, _device="/job:localhost/replica:0/task:0/device:CPU:0"](leaky_re_lu_59/sub/aquant, up_sampling2d_1/mul)]]

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/vai_q_tensorflow", line 10, in
sys.exit(run_main())
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 744, in run_main
app.run(main=my_main, argv=[sys.argv[0]] + unparsed)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/platform/app.py", line 125, in run
_sys.exit(main(argv))
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 743, in
my_main = lambda unused_args: main(unused_args, FLAGS)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 539, in main
flags.skip_check)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 327, in quantize_frozen
q_config, s_config)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 276, in calibrate_frozen
sess.run(output_tensors, feed_dict)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 929, in run
run_metadata_ptr)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1152, in _run
feed_dict_tensor, options, run_metadata)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1328, in _do_run
run_metadata)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/client/session.py", line 1348, in _do_call
raise type(e)(node_def, op, message)
tensorflow.python.framework.errors_impl.InvalidArgumentError: output dimensions must be positive
[[node up_sampling2d_1/ResizeNearestNeighbor (defined at /opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py:260) = ResizeNearestNeighbor[T=DT_FLOAT, align_corners=false, _device="/job:localhost/replica:0/task:0/device:CPU:0"](leaky_re_lu_59/sub/aquant, up_sampling2d_1/mul)]]

Caused by op 'up_sampling2d_1/ResizeNearestNeighbor', defined at:
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/bin/vai_q_tensorflow", line 10, in
sys.exit(run_main())
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 744, in run_main
app.run(main=my_main, argv=[sys.argv[0]] + unparsed)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/platform/app.py", line 125, in run
_sys.exit(main(argv))
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 743, in
my_main = lambda unused_args: main(unused_args, FLAGS)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 539, in main
flags.skip_check)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 327, in quantize_frozen
q_config, s_config)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py", line 260, in calibrate_frozen
tf.import_graph_def(calib_graph_def, name='')
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/util/deprecation.py", line 488, in new_func
return func(*args, **kwargs)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/importer.py", line 442, in import_graph_def
_ProcessNewOps(graph)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/importer.py", line 234, in _ProcessNewOps
for new_op in graph._add_new_tf_operations(compute_devices=False): # pylint: disable=protected-access
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/ops.py", line 3440, in _add_new_tf_operations
for c_op in c_api_util.new_tf_operations(self)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/ops.py", line 3440, in
for c_op in c_api_util.new_tf_operations(self)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/ops.py", line 3299, in _create_op_from_tf_operation
ret = Operation(c_op, self)
File "/opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/python/framework/ops.py", line 1770, in init
self._traceback = tf_stack.extract_stack()

InvalidArgumentError (see above for traceback): output dimensions must be positive
[[node up_sampling2d_1/ResizeNearestNeighbor (defined at /opt/vitis_ai/conda/envs/vitis-ai-tensorflow/lib/python3.6/site-packages/tensorflow/contrib/decent_q/python/decent_q.py:260) = ResizeNearestNeighbor[T=DT_FLOAT, align_corners=false, _device="/job:localhost/replica:0/task:0/device:CPU:0"](leaky_re_lu_59/sub/aquant, up_sampling2d_1/mul)]]

tensorflow.python.framework.errors_impl.NotFoundError: Op type not registered 'LeakyRelu' in binary running on cb56f6cc53b2. Make sure the Op and Kernel are registered in the binary running in this process. Note that if you are loading a saved graph which used ops from tf.contrib, accessing (e.g.) tf.contrib.resampler should be done before importing the graph, as contrib ops are lazily registered when the module is first accessed.

I am trying to retrieve the N2Cube Profile results for each layer of the MobilenetV2 tensorflow model that I downloaded from Vitis-AI/AI-Model-Zoo. I expect it to show DepthwiseConv layers and an AvgPool layer, but it seems to only return Conv2D layers:

The output from dexplorer -w:

Here are the steps to recreate the issue:

1. Compile all_models/tf_mobilenetv2_imagenet_224_224_1.17G/fix/deploy_model.pb
   dnnc --parser=tensorflow --frozen_pb=fix/deploy_model.pb --output_dir=xilinx_modelzoo --dcf=../../../dcf/ZCU104.dcf --mode=debug --cpu_arch=arm64 --net_name=MobilenetV2 --save_kernel --dump=all
2. Copy over the generated ELF file to the ZCU104
3. Create a Makefile and main.cc similar to the files in ZCU104/samples/resnet50, updated with the correct DPU Kernel Name, Input Node, and Output Node
4. Run with profile mode
   dexplorer -m profile
5. Compile main.cc linked with ELF and run the generated executable

Is there a way to get the profiler to generate these results with each layer in the network?

update the ml-suite and give a ami

Hi, I want to train yolov3 model and deploy it on Xilinx dnndk，but i don't have the caffe training source code of yolov3, can you provide source code or some references?

https://github.com/Xilinx/Vitis-AI/tree/master/Vitis-AI-Library

https://www.xilinx.com/bin/public/openDownload?filename=vitis_ai_model_ZCU102_2019.2-r1.0.deb

ZCU104 model deb is ZCU102 not 104

hi,
I have configured the docker-based model quantization tool (CPU version). However, I encountered the following problems when I fixed the detection model.

When I ran a problem query in the xilinx community, I found the following solutions:
https://forums.xilinx.com/t5/Machine-Learning/trouble-using-decent-sh/m-p/987902#M1301
I tried it, but my problem was not solved.
I would like to know the specific form of calib.txt required for the new quantitative tool(based on caffe).
Because I tried both of the following methods and it didn't work.

0001.jpg 1
0002.jpg 1

or:

0001.jpg
0002.jpg

Hi
I am following the tutorials available at https://github.com/Xilinx/Vitis-AI/blob/master/DPU-TRD/prj/Vitis/README.md.In the section "5.2.1 Building the hardware Design", when I run the "% make KERNEL=DPU_SM DEVICE=zcu102" to build the hardware, I can see the bit file is generated, but I receive the following error after that:

ERROR: [v++ 82-29] Exception in main() -- ERROR: [v++ 17-70] Application Exception: Not found in path: xclbinutil
Makefile:70: recipe for target 'binary_container_1/dpu.xclbin' failed

Here is the terminal screen for the related error:

[19:11:05] Starting bitstream generation..
[19:13:06] Creating bitmap...
[19:13:37] Writing bitstream ./zcu102_base_wrapper.bit...
[19:13:37] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 02m 31s
[19:13:37] Run vpl: Step impl: Completed
[19:13:38] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [19:13:38] Run run_link: Step vpl: Completed
Time (s): cpu = 00:36:26 ; elapsed = 00:49:59 . Memory (MB): peak = 684.215 ; gain = 0.000 ; free physical = 54560 ; free virtual = 63819
INFO: [v++ 60-1443] [19:13:38] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/address_map.xml -sdsl /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -xclbin /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -rtd /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd -o /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml
INFO: [v++ 60-1618] Launching
INFO: [v++ 60-1441] [19:13:40] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 684.215 ; gain = 0.000 ; free physical = 54561 ; free virtual = 63821
INFO: [v++ 60-1443] [19:13:40] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/system.bit --force --key-value SYS:mode:flat --add-section :JSON:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_xml.rtd --add-section BUILD_METADATA:JSON:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_build.rtd --add-section EMBEDDED_METADATA:RAW:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml --add-section SYSTEM_METADATA:RAW:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_zcu102_zcu102_base_1_0 --output /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /opt/AI/Vitis-AI/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
ERROR: [v++ 82-29] Exception in main() -- ERROR: [v++ 17-70] Application Exception: Not found in path: xclbinutil

Makefile:70: recipe for target 'binary_container_1/dpu.xclbin' failed
make: *** [binary_container_1/dpu.xclbin] Error 1
root@hpn118:/opt/AI/Vitis-AI/DPU-TRD/prj/Vitis#

Could you please advise me how to resolve this issue?

I would greatly appreciate if someone answer my query.

Thank you.

I am quantizing cf_resnet50 by typng the command "vai_q_caffe quantize -model float.prototxt -weights float.caffemodel" and I face the following errors. Not sure how to rectify it. I'd be thankful if someone can tell where i am going wrong and how to resolve this issue.

Running any of the examples from vitis_ai_samples_zcu104 below results in a black screen and screen entering sleep mode.

• adas_detection
• resnet50
• resnet50_mt_py
• inception_v1
• video_analysis
• segmentation

The pose_detection example however completes successfully and the video_analysis example runs for a few seconds before the screen enters sleep mode as well.

All examples were tested straight from ZCU104 terminal, not over ssh with X11 forwarding!

Steps to Reproduce

1. From within the Vitis-AI runtime docker container, cross-compile all vitis_ai_samples_zcu104 and transfer to board. Including any necessary test images in a folder dataset within each example dir as outlined in [UG1414, page 28].(https://www.xilinx.com/support/documentation/sw_manuals/vitis_ai/1_0/ug1414-vitis-ai.pdf)
2. Connect DP capable screen and peripherals (usb-hub, mouse, keyboard)
3. Run one of the examples outlined above:
   a. ./resnet50 dpuv2_rundir
   b. python3 resnet50.py {thread_number} dpuv2_rundir
   c. python3 inception_v1.py {thread_number} dpuv2_rundir
   d. etc
4. Screen looses connection instantly and enters sleep mode.

No logs are available in /var/log/ apart from boot logs. Tried different monitors and display port cables.

Specifications

• Version: Vitis-AI Release 1.0 9368815
• Platform: ZCU104 (HW-Z1-ZCU104 Rev1.0)
• Board Image: xilinx-zcu104-dpu-v2019.2img.gz

Related issues

Seem related to issue #31 described by @Morett07.

To run this https://github.com/Xilinx/Vitis-AI/tree/master/alveo example in the nimbix i have give to github repo for dockerfile and json file.
So which repo i can use?

Hi,

I am trying to quantize a tensorflow model with bit and activation widths set to 16 instead of 8, hoping to increase the final top-1/top-5 accuracies. However, when I tried this by calling vai_q_tensorflow and included --weight_bit 16 --activation_bit 16, the final accuracies were close to 0. I was wondering why this happened?

Any help is appreciated.

Thanks,

Problem

I am adding complex number support to PyTorch on the FPGA and I rely heavily on the ability to pass multiple samples to the FPGA at the same time using your WideType Single-Instruction, Multiple Data (SIMD) container. For a 512-bit memory bus, I would like to stream the following using my SIMD Vec<T, LOG2BW> Container:

real float: [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15]
complex float[2]: [R0, I0, R1, I1, R2, I2, R3, I3, R4, I4, R5, I5, R6, I6, R7, I7]
quaternion float[4]: [R0, I0, J0, K0, R1, I1, J1, K1, R2, I2, J2, K2, R3, I3, J3, K3]

Background

The complex/quaternion support is needed for RF/Optical communications. I have seen a wide variety of complex number support in the HLS documentations

|      Type                       |     Synthesis             |          Simulation        |
--------------------------------------------------------------------------------------------
|      std::complex <ap_fixed <>> |             YES           |              YES           |
|      std::complex<float>        |              NO           |              YES           |
|      std::complex<double>       |              NO           |              YES           |
|      complex_wrapper<float>     |              NO           |              YES           |
|      complex_wrapper<double>    |              YES          |              YES           |

The first three support the R, I, R, I memory format, while the last 2 support R, R, I, I memory format.

Proposed Solution

Now that Xilinx Vitis allows us to use Vectorized SIMD container datatypes (see WideType), there should be a built in way to treat std::complex data as a float[2] and std::quaternion as float[4]. If this idea works, the PL code wouldn't need to support std::complex<T> containers (which it currently doesn't).

I have written a blog about this:
pytorch-for-fpga-part-1-heterogeneous-processing
pytorch-for-fpga-part-2-basic-fpga-optimizations
pytorch-for-fpga-part-3-advanced-fpga-optimizations
pytorch-for-fpga-part-4-deploying-pytorch-kernels
pytorch-for-fpga-part-5-complex-and-quaternion-numbers(Coming Soon)

In Part-4 of this blog, SIMD has weird profile performance and it doesn't compile at all when the number of CUs is greater than 1. Here are some questions:

1. Does the hw_emu of WideType predict the kernel duration time accurately (see Detail)? Can you provide an Example?
2. Does the WideType data container work with Multiple Compute Units (CU)? Can you provide an Example?
3. Do you see any long-term problems with supporting complex numbers in this way? Are there potential Bottlenecks? I'm still pretty new to this.

Detail

Here are some logs. Vec<float, 0> (2^0 = 1) achieves the same hw_emu speed as float, which is expected. The Iteration intervals make sense. I'm not sure how to calculate the depth, but the duration of these math kernels seems to go up and down arbitrarily.

float duration 0.063ms
INFO: [v++ 204-61] Pipelining loop 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz

Vec<float, 0>  duration 0.062ms
INFO: [v++ 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints.
INFO: [v++ 204-61] Pipelining loop 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 14.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz

Vec<float, 1> duration 0.204ms
INFO: [v++ 204-61] Pipelining loop 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 2, Final II = 2, Depth = 11.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 2, Final II = 2, Depth = 15.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 2, Final II = 2, Depth = 9

Vec<float, 2> duration 0.178ms
INFO: [v++ 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 13.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 4, Final II = 4, Depth = 11.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz

Vec<float, 3> duration 0.205ms
INFO: [v++ 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 17.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 21.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 8, Final II = 8, Depth = 15.
INFO: [v++ 200-789] **** Estimated Fmax: 411.02 MHz

Vec<float, 4> duration 0.144ms
INFO: [v++ 204-61] Pipelining loop 'read'.
INFO: [v++ 204-61] Pipelining result : Target II = 16, Final II = 16, Depth = 25.
INFO: [v++ 204-61] Pipelining loop 'vadd'.
INFO: [v++ 204-61] Pipelining result : Target II = 16, Final II = 16, Depth = 29.
INFO: [v++ 204-61] Pipelining loop 'write'.
INFO: [v++ 204-61] Pipelining result : Target II = 16, Final II = 16, Depth = 23.

Please check the Vitis AI Forum before posting questions here. We have a community of experts and users on the Vitis AI forum ready to help you with all your questions!

Vitis AI Forum

tf_yolov3_voc_416_416_65.63G have exists;

can you share the tensorflow-yolov3-coco dataset models ?

hi，I've been training cf_fpn_cityscapes_256_512_8.9G models myself recently.
Because of the problem of my hardware resources（2080ti）, when I trained the dataset（cityscapes）,batch size could only be set to 1.
However, when batch size=1, the loss value of the model remains at 2.9 and does not decrease.
So I wanted to try to set a larger batch size by reducing the image size（from 1024x2048 to 256x512） of the dataset.As follows：

But when I used the scaled atlas to train FPN, I encountered the following bug：

Therefore, I am confused. The questions I am not sure about are as follows：
1.If the input size of the model is 256*512, it is ok for me to scale the image of the training, but why is the error reported？
2.What is the meaning of line 77of the file：“./cf_fpn_cityscapes_256_512_8.9G/code/ReadMe.md”?

Hello -

My research group is trying to use Graph Neural Networks with Alveo cards and I noticed that the tools provided don't provide the flexibility we need.

I'm right now trying to quantitize a model that takes 4 different inputs with different shapes but the tensorflow tool (vai_q_tensorflow quantize) seems to only like to receive input shapes in 4 dimensions such as: ?,a,b,c. This is ideal for images but not for what we want to do.

I checked the source code and this seems to be hard-coded. Are there plans to expand the tools to include other input shapes?

As an example, this is the input shape I need for the GNNs we use: ?,3 : ?,4 : ? : ?

Thanks!

I have a 40 thread Xeon CPU and the build time is too slow

INFO: [v++ 60-791] Total elapsed time: 1h 46m 14s

The command I used:
$ make KERNEL=DPU_SM DEVICE=zcu102

My question is: Does this have multithreading enabled by default?

Traceback (most recent call last):
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/threading.py", line 916, in _bootstrap_inner
self.run()
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/threading.py", line 864, in run
self._target(*self._args, **self._kwargs)
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/site-packages/vai/dpuv1/rt/xsnodes/stream.py", line 123, in execute
pub = self.get_pub()
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/site-packages/vai/dpuv1/rt/xsnodes/base.py", line 193, in get_pub
return xstream.Publisher(use_context=self.context)
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/site-packages/vai/dpuv1/rt/xstream.py", line 198, in init
super(Publisher, self).init(path)
File "/opt/vitis_ai/conda/envs/vitis-ai-neptune/lib/python3.6/site-packages/vai/dpuv1/rt/xstream.py", line 121, in init
self.pclient = plasma.connect(path)
File "pyarrow/_plasma.pyx", line 846, in pyarrow._plasma.connect
File "pyarrow/_plasma.pyx", line 290, in pyarrow._plasma.plasma_check_status
File "pyarrow/error.pxi", line 80, in pyarrow.lib.check_status
pyarrow.lib.ArrowIOError: Could not connect to socket /tmp/plasma-xlnx-vitis-ifpga

when I make the caffe_xilinx(use cmake ..), I meet some problems, and finally I can make all successfully, but when I try to make runtest, some problem happens.Problems like "can not find files " happend when compile test_conv_bn_fixed_layer and test_crypto.So I remove the test_conv_bn_fixed_layer.cpp and test_crypto.cpp, the problems disapper.
but then, make runtest have such errors：
[----------] 1 test from LayerFactoryTest/0, where TypeParam = caffe::CPUDevice
[ RUN ] LayerFactoryTest/0.TestCreateLayer
F1219 15:40:15.665498 12839 db_leveldb.cpp:16] Check failed: status.ok() Failed to open leveldb
IO error: /LOCK: Permission denied
*** Check failure stack trace: ***
@ 0x7f94c81335cd google::LogMessage::Fail()
@ 0x7f94c8135433 google::LogMessage::SendToLog()
@ 0x7f94c813315b google::LogMessage::Flush()
@ 0x7f94c8135e1e google::LogMessageFatal::~LogMessageFatal()
@ 0x7f94c8e447b3 caffe::db::LevelDB::Open()
@ 0x7f94c9129b25 caffe::DataReader<>::Body::InternalThreadEntry()
@ 0x7f94c8de07f5 caffe::InternalThread::entry()
@ 0x7f94c879d5d5 (unknown)
@ 0x7f94c835e6ba start_thread
@ 0x7f94bdcdf41d clone
@ (nil) (unknown)
Aborted (core dumped)
src/caffe/test/CMakeFiles/runtest.dir/build.make:57: recipe for target 'src/caffe/test/CMakeFiles/runtest' failed
when I try to train the mobilenetV2 ssd in my own dataset, errors Check failed: background_label_id != label (0 vs. 0) Found background label in the dataset happened. but use the original caffe ssd to train the same dataset, no errors. I wonder how I can train my own dataset in caffe_xilinx?

Hello,

Could you please let me know where can we download Vitis AI Optimizer, together with usage instruction?

Best,
Karlis

Hi @wilderfield ,
Installed provided xbutler package.(under alveo/package/ubuntu)
How to solve this error?

Speaking to Butler 
Response from Butler is: 
errCode: errCode: 3
errCode String: NO_FREE_RESOURCE
myHandle: 0
valid: 1

Hi Team,
We are facing an issue while installing the Vitis-AI in our system. When we run ./docker_build.sh from Load&Run Docker Container section, The system through an error message every time. Please find the screenshot of the error message.

We have tried on both ubuntu18.04 and 16.04.
Please guide me to resolve the issue.
Thanks & Regards,
Shijin Bose
[email protected]

Hi,
I try to use vai_q_caffe to do a caffe model quantization. the final message is
W1219 00:02:05.692003 91 convert_proto.cpp:1401] [DEPLOY WARNING] Layer data's output blob is all zero, this may cause error for DNNC compiler. Please check the float model.
I1219 00:02:05.696166 91 decent_q.cpp:399] Deploy Done!

Does this will has some side effect?

BR, Akio

I try to import DPU ip into vivado IP Catalog via Settings->IP->Repository, and I select the IP location at Vitis-AI-master/DPU-TRD/dpu_ip/dpu_eu_v3_1_0, however, warning comes that 'Cannot get enviroment domain name variable for the component vendor name. Setting the vendor name to 'user.org'', then I failed to import the ip to the catalog. Am i do it in a wrong way? thank you.

Is Vitis supported other Zynq-7000 platform except the platforms listed in the tutorial?