yosyshq Goto Github PK

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abc

ABC: System for Sequential Logic Synthesis and Formal Verification

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

arachne-pnr

Place and route tool for FPGAs

eqy

Equivalence checking with Yosys

fpga-toolchain

Multi-platform nightly builds of open source FPGA tools

furo-ys

A clean customizable documentation theme for Sphinx

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

marlann

Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks

mau

Modular Application Utilities

mcy

Mutation Cover with Yosys (MCY)

nerv

Naive Educational RISC V processor

nextpnr

nextpnr portable FPGA place and route tool

nextpnr-bench

Benchmarks for nextpnr

nextpnr-tests

oss-cad-suite-build

Multi-platform nightly builds of open source digital design and verification tools

padring

A padring generator for ASICs

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

prjtrellis-db

Project Trellis database

pyosys-tests

pyosys tests

riscv-formal

RISC-V Formal Verification Framework

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

sby-gui

GUI for SymbiYosys

scy

Sequence of Covers with Yosys

setup-oss-cad-suite

Set up your GitHub Actions workflow with a OSS CAD Suite

sublime-yosys

Yosys syntax highlighter for the Sublime Text 3 editor

vloghammer

A Verilog Synthesis Regression Test

yosys

Yosys Open SYnthesis Suite

yosys-bench

Benchmarks for Yosys development