EDIF backend result rejected by Xilinx about yosys HOT 3 CLOSED

If I comment out the hadder u0 instantiation, then the edif produced is correct, and accepted by the Xilinx toolchain.

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The problem here was that the instantiation of hadder used positional arguments and edif does not. I've now added a feature to the hierarchy pass (enabled by default) that transforms positional arguments to arguments using the proper port names. It seems to work now (tested with ISE 14.5).

Interestingly, if I don't use synth_xilinx but instead simply write the RTL netlist to the EDIF file, edif2ngd just segfaults with any useful error message. Maybe because the netlist contains cell types that the Xilinx tools do not recognize? I'm not going to further investigate this, but it does not improve the level of confidence I have in edif2ngd.. ;-)

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Ok, thanks for adding the feature, i'll continue my tutorial on adders now.

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