Spurious warnings "select out of bounds on signal" when there is no such thing ... about yosys HOT 1 OPEN

module top (
	output reg  [31:0] rd_data,
	input  wire [31:0] wr_data
);
	// Signals
	// -------
	wire [31:0] mem_do_w;
	reg  [31:0] mem_di_w;

	// Map input data to/from 16*NW bit words
	always @(*)
	begin : map
		integer n, x, o;

		// Map actual bits
		for (n=0; n<8; n=n+1)
		begin
			// Determine position
			x = n % 2;	// Which SPRAM
			o = n / 2;	// Which nibble inside that SPRAM

			mem_di_w[(16*x)+(4*o)+:4] =  wr_data[4*n+:4];
			rd_data[4*n+:4] = mem_do_w[(16*x)+(4*o)+:4];
		end
	end
endmodule