Comments (2)
SystemVerilog packages only have very limited support in the verilog front end, so I suspect this is related.
from yosys.
You could try https://github.com/zachjs/sv2v, which has full support for SystemVerilog packages.
from yosys.
Related Issues (20)
- Should -nomx8 be the default for the GateMate?
- opt: no "-purge" option but public names removed HOT 2
- Tests fails on Debian GNU/Linux on ppc64 HOT 6
- write_smt2: "-wires" option leads to inequivalent descriptions
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
- Inout can't be read with constant value HOT 3
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
- Unexpected Result from `synth_gowin` Pass HOT 4
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells) HOT 3
- Build error: `make: *** [Makefile:810: abc/abc] Error 2` HOT 4
- Documentation is unreadable if the system theme is dark HOT 5
- Wired-or (wor) wires generate $or / $reduce_or cells in output HOT 3
- Nothing of abc folder contents at git clone https://github.com/YosysHQ/yosys.git HOT 1
- Yosys seems to handle bit operations on empty strings inconsistently with the original design. HOT 4
- The negation operation on an empty string results in an exception. HOT 6
- Outputs differ before and after synthesis, but Yosys seems correct.
- read_verilog doesn't respect `signed` keyword HOT 2
- make error 'abc' is not configured as a git submodule. HOT 12
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from yosys.