Comments (7)
Verilog parameters must be contained within a module. I had a quick look into the SystemVerilog spec and it does not look like they allow parameters outside of modules either...
But maybe I'm wrong.. What makes you believe that verilog parameters outside a module are allowed in Verilog? What would the intended behavior of that be?
Closing the issue now. I'll reopen it if it turns out there is more to it..
from yosys.
Well, both Vivado and Verilator supports it, so I just naively assumed that it is valid. Of course, this does not mean that it is in the standard.
from yosys.
both Vivado and Verilator supports it
interesting. Icarus Verilog, GPLCver, Veriwell, Verific, and Synplify Pro produce errors for this. Riviera-PRO and VCS seem to accept parameters outside of modules.
Looking at the IEEE 1800-2012 Std. document again it looks like parameter
declarations (as well as localparam
declarations) are package items and package items can be used in the global context. So I have now added support for that in commit ba4cce9.
Thanks for bringing this to my attention.
from yosys.
Excellent - then I don't need to change my code right away, thanks!
From what you say, it sounds like it is left undefined in the standard, so probably I should get rid of global parameter definitions.
Thanks again.
from yosys.
it sounds like it is left undefined in the standard
Well, it's definitely not part of Verilog 2005. But it is part of SystemVerilog 2012 and seems to be well-defined.
However, I wonder if you are using parameter
when in fact you'd only need localparam
. (parameter
can be overwritten at module instantiation, localparam
is just a name for a constant value.)
from yosys.
Well, it's definitely not part of Verilog 2005. But it is part of SystemVerilog 2012 and seems to be well-defined.
Weird I did not think that SystemVerilog for Vivado was enabled by default.
Probably I could use localparam
as well. I am fairly inexperienced with Verilog and as I've picked it up quite quickly, I probably have developed one or more bad habits along the way. Basically what I am doing is following: I have a unit with a UART serial interface with N-bit instructions. As I continue to extend the code, I add more and more instructions which in turn means number of bits to describe an instruction increases - to avoid spreading instruction codes and instruction format all over the code, I have nicely gathered this in one file. Feel free to come with suggestions on how you would go about this.
from yosys.
Just a last comment on this one:
Vivado seems to be using SystemVerilog 1800-2009 and for Verilator the code compiles with SV 1800-2005, but not with 1364-2005. Verilator does at no point complain about the global scope parameters, but only other things.
from yosys.
Related Issues (20)
- induction: engine_0/logfile_induction.txt does not tail with a 'Status: failed' entry when appropiate
- ABC bundled with yosys-0.29 release fails to build: error: ‘intptr_t’ was not declared in this scope; did you mean ‘abc::intptr_t’? HOT 1
- Warning for nets with multiple drivers HOT 2
- CXXRTL: "Assert `!for_debug' failed" caused by the "-noflatten" option HOT 2
- techmap: $DFFSR_NPN_ with combinational logic instead $DFFSR_NNN_
- Issue while running make test HOT 1
- Exhaustive if statement generates latches
- Exhaustive if statement generates latches HOT 3
- DLatches do not synthesize in AIGER HOT 2
- Synthesis bug or maybe wrong understanding HOT 2
- Yosys fails to parse "endmodule;" due to a semicolon HOT 2
- Improve detection of multiply declared signals in SV frontend HOT 1
- CXXRTL: incorrect result of shl operator HOT 1
- CXXRTL: bus error when performing the ">>>" operation
- abc commit 0d0063f7 breaks tests/arch/ice40/rom.ys HOT 6
- SV Type parameters are not supported HOT 1
- FSM Extraction does not work HOT 3
- Extraction of FSM from VHDL HOT 6
- part-selects (`$shift`, `$shiftx`) create huge MUX-trees HOT 25
- How to figure out the actual name of the flipflop in yosys? HOT 4
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from yosys.