Comments (1)
Only compatible declarations should pass this block, so now that conflicts with constant drivers are better detected in check this should only accept relatively "harmless" mistakes, but maybe someone can figure out how to add some checks on the declaration there.
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Related Issues (20)
- Parameters in other packages HOT 2
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
- Latch inferred for x signal HOT 4
- Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855
- Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors HOT 3
- Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports HOT 1
- Another out-of-memory problem with for loop
- synth_* passes should call `check -mapped`
- "ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design HOT 2
- Crash in yosys-abc HOT 1
- Manual title page should have yosys version number
- Should -nomx8 be the default for the GateMate?
- opt: no "-purge" option but public names removed HOT 2
- Tests fails on Debian GNU/Linux on ppc64 HOT 6
- write_smt2: "-wires" option leads to inequivalent descriptions
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
- Inout can't be read with constant value HOT 3
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
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from yosys.