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mips

A MIPS processor, implemented in C.

mips--

A dual core MIPS subset CPU written in behavioral, synthesizable VHDL

mips-1

mips-2

A simple implementation of MIPS I

mips-3

A MIPS processor in VHDL for FPGA and ASIC

mips-4

611 CPU

mips-5

A synthesizable soft processor based upon the MIPS instruction set

mips-architecture-cpu-design-based-on-fpga

基于FPGA的MIPS架构的CPU设计

mips-baremetal

gcc toolchain for mips 4kc/p/m processor with no OS

mips-core-verilog

Automatically exported from code.google.com/p/mips-core-verilog

mips-cpu

MIPS CPU implemented in Verilog

mips-cpu-system

my mips cpu design in vhdl. support vga and PS/2 keyboard

mips-processor

UCSD CSE 141L Spring 2013 MIPS processor assignment.

mips-processor-1

5 Cycle-accurate Implementation of a pipelined MIPS processor

mips-processor-2

The project is to build a MIPS micro-processor, which is composed of registers, ALUs, finite state machines, memories, and other logic building blocks. The microarchitecture can be separated into two parts: the datapath and the control. The datapath contains structures such as memories, registers, ALUs, and multiplexers. The control unit receives the current instruction from the datapath and tells the datapath how to execute that instruction.

mips-verilog

Implemented 5-stage pipelined Microprocessor using Verilog

mips-verilog-1

MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.

mips32

A MIPS32 CPU implemented by VHDL

mips32r1

MIPS32 implementation in Verilog published on OpenCores, written by Grant Ayers

mips32r1_core

A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.

mips32r1_ml605

small porting of mips32r1

mips32r1_soc_nano

A MIPS32 System-on-Chip for the DE0-Nano FPGA

mips32r1_xum

A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA. (Old University of Utah XUM archive)

mips64-verilog

A basic implementation of a single-cycle MIPS 64-bit CPU

mipsc

An ANSI C compiler for the MIPS microarchitecture

mipscore

32 Bit MIPS processor with bypassing and forwarding done in Verilog

mipscpu

mipscpu-1

A six pipelined (Fetch, Decode, Issue, Execute, Memory, WriteBack) cpu that only implements parts of mips instructions in Verilog

mipscpu2

The second generation of MIPS CPU with pipelined design

mipsfpga-plus

A Verilog interface that allows downloading HEX files from PC to FPGA board using PuTTY, USB on PC and UART on FPGA board