johonkanen / ac_inout_psu Goto Github PK

Miss some sort of simulation framework/testbench. Any plan?
I have successfully compiled source code with GHDL and I have implemented the design with QuartusII Lite 20.1.1

since the ethernet is managed, the mdio interface needs control

it was noticed that the spi adc does not convert every time.

No known sure way to reproduce bug, following might trigger it

1. reset hw with power supply
2. reprogram
3. ad conversion might not be presetn

Rgmii ethernet transmitter is needed

create uart to communicate with fpga

• add uart sources
• route uart io to control card pins
• test uart with some generic data

• 18x18 signed multiply
• 18/18 signed divide
• sin and cos
• test with hardware

code with multiple successive sequential_multiply calls does not function as intended. There seems to be a bug with code failing to prevent further multiplications to be pipelined when sequential_multiply is called.

Initial test with uart suggests that the io sampling point is not correct as there is a lot of noise present in the measurement

The source\math_library\multiplier\simulation\sim_miltiplier.bat simulation batch seems not working in my case.

Setting of project_root variable doesn't work and it is not used anyway.

If I remove all unused or problematic stuff and keep it to the base bone, I still have issue with VCD.

I am working on a Windows 10 machine with GHDL/Gtkwave.

Create initial project and set up build

current state variable is actually just an integrator and a trigger mechanism is needed for it to be usable as a real state variable. Trigger should be added for the state variable

• Add ethernet sources
• add mdio
• test mdio with hardware
• test ethernet frame receiver with hardware