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Import mechanism in litex_boards.target hides errors in imported files
The bare except at
litex-boards/litex_boards/targets.py
Line 11 in 2a0fbca
target.py file has any errors in it, you will get a weird error about the file not existing.
Really you should just be catching ModuleNotFound exceptions. See patch below;
diff --git a/litex_boards/targets.py b/litex_boards/targets.py
index 8ae7041..293e35b 100644
--- a/litex_boards/targets.py
+++ b/litex_boards/targets.py
@@ -8,7 +8,7 @@ class Targets:
for support in ["official", "partner", "community"]:
try:
return importlib.import_module("litex_boards." + support + ".targets." + name)
- except:
+ except ModuleNotFoundError:
pass
raise ModuleNotFoundError
If you have an error in your target file now, you get an exception like you expected.
kc705 doesn't build with --integrated-main-ram-size set
Looks like SoCCore adds main_ram as a region already and kc705.py trys to add_sdram separately. What is the recommended way? Thanks!
$ python kc705.py --integrated-main-ram-size 0x100000 --build
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2021-02-25 09:25:33)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7k325t-ffg900-2.
INFO:SoC:System clock: 125.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x00100000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:RAM main_ram added Origin: 0x40000000, Size: 0x00100000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 3.
INFO:SoCCSRHandler:uart CSR allocated at Location 4.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S7MMCM:Creating S7MMCM, speedgrade -2.
INFO:S7MMCM:Registering Differential ClkIn of 200.00MHz.
INFO:S7MMCM:Creating ClkOut0 sys of 125.00MHz (+-10000.00ppm).
INFO:S7MMCM:Creating ClkOut1 sys4x of 500.00MHz (+-10000.00ppm).
INFO:S7MMCM:Creating ClkOut2 idelay of 200.00MHz (+-10000.00ppm).
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 6.
@#$@#$ sdram made it here
INFO:SoCCSRHandler:sdram CSR allocated at Location 7.
ERROR:SoCBusHandler:main_ram already declared as Region:
ERROR:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (3)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x00100000, Mode: RW, Cached: True Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- main_ram
Traceback (most recent call last):
File "kc705.py", line 178, in <module>
main()
File "kc705.py", line 160, in main
soc = BaseSoC(
File "kc705.py", line 77, in __init__
self.add_sdram("sdram",
File "/home/w/software/litex/litex/litex/soc/integration/soc.py", line 1248, in add_sdram
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
File "/home/w/software/litex/litex/litex/soc/integration/soc.py", line 170, in add_region
raise
zybo_z7: ENET0_MDIO : must be mio instead of EMIO and SDIO0 WP is not available
According to the schematic MDIO (MDC, MDIO) must be connected to PS_MIO052_501 and PS_MIO053_501 respectivelly.
In xci file the line 607 is wrong:
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO">EMIO</spirit:configurableElementValue>
and must be
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_ENET0_GRP_MDIO_IO">MIO 52 .. 53</spirit:configurableElementValue>
SDIO_WP in not used
line 666:
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0">1</spirit:configurableElementValue>
and line 1118
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_IO">EMIO</spirit:configurableElementValue>
must be
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_EN_EMIO_WP_SDIO0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_ENABLE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PCW_SD0_GRP_WP_IO"><Select></spirit:configurableElementValue>
I would be appy to apply by myself this change but I don't know how to provide modified file since it isn't under version control.
ULX3S: Adding spiflash, U3 pinout error
Not sure if I should open this issue here, or on some other ULX3S repo...
I'm attempting to add the onboard SPI flash to the ULX3S board to enable my SoC to boot from flash (See initial WIP commit here: blakesmith@2859975#diff-0d05f744fae28b2e373b10e5bc6eda679ce414f074620c726c5044e1071ed72eR87). Relevant snippet is here:
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("R2")),
Subsignal("clk", Pins("U3")),
Subsignal("miso", Pins("V2")),
Subsignal("mosi", Pins("W2")),
Subsignal("wp", Pins("Y2")),
Subsignal("hold", Pins("w1")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("R2")),
Subsignal("clk", Pins("U3")),
Subsignal("dq", Pins("W2", "V2", "Y2", "W1")),
IOStandard("LVCMOS33")
),I followed the schematics here, but the "U3" pin is not present in the CABGA381 package, and get a constraint error:
Info: Packing IOs..
Info: pin 'clk25$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'oled_ctl_csn$tr_io' constrained to Bel 'X0/Y89/PIOA'.
Info: pin 'oled_ctl_dc$tr_io' constrained to Bel 'X0/Y92/PIOA'.
Info: pin 'oled_ctl_resn$tr_io' constrained to Bel 'X0/Y92/PIOB'.
Info: pin 'oled_spi_clk$tr_io' constrained to Bel 'X0/Y92/PIOD'.
Info: pin 'oled_spi_mosi$tr_io' constrained to Bel 'X0/Y92/PIOC'.
Info: pin 'rst$tr_io' constrained to Bel 'X4/Y95/PIOA'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X126/Y89/PIOA'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X126/Y38/PIOC'.
Info: pin 'sdram_clock$tr_io' constrained to Bel 'X126/Y38/PIOB'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X126/Y86/PIOA'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X126/Y86/PIOB'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X126/Y86/PIOC'.
Info: pin 'serial_rx$tr_io' constrained to Bel 'X0/Y89/PIOB'.
Info: pin 'serial_tx$tr_io' constrained to Bel 'X0/Y56/PIOC'.
ERROR: IO pin 'spiflash_clk$tr
_io' constrained to pin 'U3', which does not exist for package 'CABGA381'.
ERROR: Packing design failed.
Here's a screenshot from schematic as well:
I validated that that pin does not exist in the latest Trellis DB:
blake@blake-XPS-13-9360:~/src/prjtrellis/database/ECP5/LFE5UM5G-85F$ cat iodb.json | jq .packages.CABGA381.U3
null
I can't seem to find an ECP5 caBGA381 pinout diagram (just spreadsheets / CSVs) to see if the pin just has a different name from the footprint used on the board, from the one it's actually tied to.
Any advice on how to proceed here? This seem unlikely to be an issue in the Trellis Database (though it could be!) Happy to open this on a ULX3S repo if that's more appropriate.
Thanks so much for LiteX! I'm really enjoying exploring it so far.
`litex_boards.partner.targets` depends on liteeth
When importing something from litex_boards.partner.targets, all boards are imported. This adds a dependency on liteeth where one is not necessary.
xobs@nas /d/x/f/litex> ./workshop.py --board pvt
lxbuildenv: v2019.8.19.1 (run ./workshop.py --lx-help for help)
lxbuildenv: Skipping git configuration because "skip-git" was found in LX_CONFIGURATION
lxbuildenv: To fetch from git, run ./workshop.py --board pvt --lx-check-git
Traceback (most recent call last):
File "./workshop.py", line 17, in <module>
from litex_boards.partner.targets.fomu import _CRG
File "/disk/xobs-data/fomu-workshop/litex/deps/litex_boards/litex_boards/partner/targets/__init__.py", line 1, in <module>
from litex_boards.partner.targets import netv2
File "/disk/xobs-data/fomu-workshop/litex/deps/litex_boards/litex_boards/partner/targets/netv2.py", line 19, in <module>
from liteeth.phy.rmii import LiteEthPHYRMII
ModuleNotFoundError: No module named 'liteeth'
xobs@nas /d/x/f/litex>
RAM and Ethernet support for Zybo
I was working with the Zybo 7z020 and am not sure if there is an easy way to add an ethernet port (for the wishbone-tool) and the RAM to my target (which is using a softcore on the PL).
As I still am fairly new in all of this I wondered if you can provide me with some insights.
- The zybo_z7 platform introduces ps7_mio and ps7_ddram as extensions without ever specifying concrete Pins, how does that work?
- As the ethernet port is directly connected to a PS controller (which may be accessible over ps7_mio?) is there an easy way add this to a target?
- The Zybo Rev. b 7z020 platform and target I created have the same functionality as the ones for the zybo rev. A which you added here, should I work on a pull-request for that?
Arty: bios with ethernet support does not fit into ROM
running:
python3 litex-boards/litex_boards/targets/arty.py --with-ethernet
fails with:
riscv64-unknown-elf-ld: bios.elf section `.rodata' will not fit in region `rom'
riscv64-unknown-elf-ld: region `rom' overflowed by 1608 bytes
@enjoy-digital did the default ROM size shrink recently, or the binary got bigger?
EthernetSoC for Intel FPGA?
there seem to be no ethernet enabled target for any Intel platform? What is the best way to create one? doing a copy of EthernetSoC from arty to C10LP platform does compile but ethernet seems to be dead, at least no packets are transmitted.
Missing dependencies
The current setup.py does not list any dependencies but litex-boards does depend on migen, litex and a bunch of litex modules.
uart_name="jtag_atlantic", # not working any more?
uart_name="jtag_atlantic",
it used to work, but now throws duplicate name error, any new syntax needed?
TypeError: init() got multiple values for keyword argument 'uart_name'
vcu118 target with vexriscv_smp causes vexriscv to fail
Not sure if this is the right repo for this issue. Please let me know if I should repost this issue to another repo.
When running this command ./vcu118.py --build --cpu-type vexriscv_smp --cpu-variant linux
Litex will attempt to generate the following file: VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ldw512.
Vexriscv uses the following command from the dev branch:
vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen --cpu-count=1 --ibus-width=32 --dbus-width=32 --dcache-size=4096 --icache-size=4096 --dcache-ways=1 --icache-ways=1 --litedram-width=512 --aes-instruction=False --netlist-name=VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ldw512 --netlist-directory=/home/will/research/softcore/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog
However, VexRiscv fails with the following error during this process:
[info] Step 14
[info] Build dBusCoherent
[info] Build dBusCoherent_bmb_slaveModel_invalidationGen
[info] Build
[info] Step 15
[info] Build cores_0_cpu_dBus_connector_invalidationPlanner
[info] Build dBusCoherent_bmb_slaveModel_arbiterGen
[info] Build cores_0_cpu_dBus_masterModel_invalidationRequirementsGen2
[info] Step 16
[info] [Progress] at 1.145 : Checks and transforms
[error] Exception in thread "main" spinal.core.SpinalExit:
[error]
[error] ********************************************************************************
[error] ********************************************************************************
[error] WIDTH MISMATCH on (toplevel/iBridge_logic/io_input_upSizer_io_output_unburstify/buffer_beat : UInt[0 bits]) := (UInt - UInt)[1 bits] at
[error] spinal.lib.bus.bmb.BmbUnburstify$$anon$2$$anonfun$1.apply$mcV$sp(BmbUnburstify.scala:40)
[error] spinal.lib.bus.bmb.BmbUnburstify$$anon$2.(BmbUnburstify.scala:39)
[error] spinal.lib.bus.bmb.BmbUnburstify.(BmbUnburstify.scala:28)
[error] spinal.lib.bus.bmb.Bmb.unburstify(Bmb.scala:552)
[error] vexriscv.demo.smp.BmbToLiteDram.(Misc.scala:166)
[error] vexriscv.demo.smp.BmbToLiteDramGenerator$$anonfun$12.apply(Misc.scala:264)
[error] vexriscv.demo.smp.BmbToLiteDramGenerator$$anonfun$12.apply(Misc.scala:264)
[error] spinal.lib.generator.Generator$Task.build(Generator.scala:216)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1$$anonfun$apply$mcV$sp$1.apply(Generator.scala:276)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1$$anonfun$apply$mcV$sp$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply$mcV$sp(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator.apply(Generator.scala:240)
[error] spinal.lib.generator.Generator.generateIt(Generator.scala:274)
[error] spinal.lib.generator.GeneratorCompiler$$anonfun$build$3.apply(Generator.scala:354)
[error] spinal.lib.generator.GeneratorCompiler$$anonfun$build$3.apply(Generator.scala:352)
[error] spinal.lib.generator.GeneratorCompiler.build(Generator.scala:352)
[error] spinal.lib.generator.GeneratorComponent.(Generator.scala:390)
[error] spinal.lib.generator.Generator.toComponent(Generator.scala:297)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.dutGen(VexRiscvSmpLitexCluster.scala:117)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$$anonfun$18.apply(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$$anonfun$18.apply(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.delayedEndpoint$vexriscv$demo$smp$VexRiscvLitexSmpClusterCmdGen$1(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$delayedInit$body.apply(VexRiscvSmpLitexCluster.scala:59)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.main(VexRiscvSmpLitexCluster.scala:59)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen.main(VexRiscvSmpLitexCluster.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] WIDTH MISMATCH on (toplevel/dBridge_logic/io_input_upSizer_io_output_unburstify/buffer_beat : UInt[0 bits]) := (UInt - UInt)[1 bits] at
[error] spinal.lib.bus.bmb.BmbUnburstify$$anon$2$$anonfun$1.apply$mcV$sp(BmbUnburstify.scala:40)
[error] spinal.lib.bus.bmb.BmbUnburstify$$anon$2.(BmbUnburstify.scala:39)
[error] spinal.lib.bus.bmb.BmbUnburstify.(BmbUnburstify.scala:28)
[error] spinal.lib.bus.bmb.Bmb.unburstify(Bmb.scala:552)
[error] vexriscv.demo.smp.BmbToLiteDram.(Misc.scala:166)
[error] vexriscv.demo.smp.BmbToLiteDramGenerator$$anonfun$12.apply(Misc.scala:264)
[error] vexriscv.demo.smp.BmbToLiteDramGenerator$$anonfun$12.apply(Misc.scala:264)
[error] spinal.lib.generator.Generator$Task.build(Generator.scala:216)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1$$anonfun$apply$mcV$sp$1.apply(Generator.scala:276)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1$$anonfun$apply$mcV$sp$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply$mcV$sp(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator$$anonfun$generateIt$1.apply(Generator.scala:275)
[error] spinal.lib.generator.Generator.apply(Generator.scala:240)
[error] spinal.lib.generator.Generator.generateIt(Generator.scala:274)
[error] spinal.lib.generator.GeneratorCompiler$$anonfun$build$3.apply(Generator.scala:354)
[error] spinal.lib.generator.GeneratorCompiler$$anonfun$build$3.apply(Generator.scala:352)
[error] spinal.lib.generator.GeneratorCompiler.build(Generator.scala:352)
[error] spinal.lib.generator.GeneratorComponent.(Generator.scala:390)
[error] spinal.lib.generator.Generator.toComponent(Generator.scala:297)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.dutGen(VexRiscvSmpLitexCluster.scala:117)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$$anonfun$18.apply(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$$anonfun$18.apply(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.delayedEndpoint$vexriscv$demo$smp$VexRiscvLitexSmpClusterCmdGen$1(VexRiscvSmpLitexCluster.scala:122)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$delayedInit$body.apply(VexRiscvSmpLitexCluster.scala:59)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.main(VexRiscvSmpLitexCluster.scala:59)
[error] vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen.main(VexRiscvSmpLitexCluster.scala)
[error] ********************************************************************************
[error] ********************************************************************************
[error] Design's errors are listed above.
[error] SpinalHDL compiler exit stack :
[error] at spinal.core.SpinalExit$.apply(Misc.scala:400)
[error] at spinal.core.SpinalError$.apply(Misc.scala:451)
[error] at spinal.core.internals.PhaseContext.checkPendingErrors(Phase.scala:174)
[error] at spinal.core.internals.PhaseContext.doPhase(Phase.scala:190)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$116.apply(Phase.scala:2431)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2$$anonfun$apply$116.apply(Phase.scala:2429)
[error] at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
[error] at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2429)
[error] at spinal.core.internals.SpinalVerilogBoot$$anonfun$singleShot$2.apply(Phase.scala:2368)
[error] at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:31)
[error] at spinal.core.internals.SpinalVerilogBoot$.singleShot(Phase.scala:2368)
[error] at spinal.core.internals.SpinalVerilogBoot$.apply(Phase.scala:2363)
[error] at spinal.core.Spinal$.apply(Spinal.scala:353)
[error] at spinal.core.SpinalConfig.generateVerilog(Spinal.scala:160)
[error] at vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.delayedEndpoint$vexriscv$demo$smp$VexRiscvLitexSmpClusterCmdGen$1(VexRiscvSmpLitexCluster.scala:122)
[error] at vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$delayedInit$body.apply(VexRiscvSmpLitexCluster.scala:59)
[error] at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
[error] at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.App$$anonfun$main$1.apply(App.scala:76)
[error] at scala.collection.immutable.List.foreach(List.scala:392)
[error] at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
[error] at scala.App$class.main(App.scala:76)
[error] at vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen$.main(VexRiscvSmpLitexCluster.scala:59)
[error] at vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen.main(VexRiscvSmpLitexCluster.scala)
[error] Nonzero exit code returned from runner: 1
[error] (Compile / runMain) Nonzero exit code returned from runner: 1
[error] Total time: 3 s, completed Jan 4, 2021, 11:14:48 AM
Colorlight-5a-75b: Optimize IP/UDP/Etherbone timings, add SDRAM
- Use 32-bit datapath for the IP/UDP Stack + Etherbone (will be posssible with current work in enjoy-digital/liteeth#21).
- Reduce
sys_clk_freq. - Integrate SDRAM.
Does the de1-soc target supports using the hard processor?
I have 8 years of experience in VLSI and EDA.
I don't have a lot of experience with FPGAs, I used my de1-soc for my final thesis at the university and haven't used it ever since.
I am very interested in contributing to open hardware projects and I think this is a nice way to do it.
SPI flash example target for Xilinx?
it seems no config or target includes spi flash module for Xilinx ?
timvideos has something but I wonder what is the most official and clean example to add normal x4 spi flash for X 7 series?
de10nano support
I have started trying to modify the de0nano for the de10nano, using the 128mb SDRAM expansion board for MiSTer, the retro console/computer/arcade emulator.
The problem I ma having is that when I use, from the documentation, the correct UART serial_rx (PIN A22) and serial_tx (PIN B21) in platforms/de10nano
("serial", 0,
Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("A22"), IOStandard("3.3-V LVTTL"))
),
I get the following errors:
Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (175020): The Fitter cannot place logic pin in region (79, 81) to (79, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): serial_rx
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended input pin locations available (1 location affected)
Info (175029): A22
Info (175015): The I/O pad serial_rx is constrained to the location PIN_A22 due to: User Location Constraints (PIN_A22) File: /home/rob/Development/Quartus/Projects/linux-on-litex-vexriscv/build/de10nano/gateware/top.v Line: 6
Info (14709): The constrained I/O pad is contained within this pin
Error (175020): The Fitter cannot place logic pin in region (79, 81) to (79, 81), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info (14596): Information about the failing component(s):
Info (175028): The pin name(s): serial_tx
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (184016): There were not enough single-ended output pin locations available (1 location affected)
Info (175029): B21
Info (175015): The I/O pad serial_tx is constrained to the location PIN_B21 due to: User Location Constraints (PIN_B21) File: /home/rob/Development/Quartus/Projects/linux-on-litex-vexriscv/build/de10nano/gateware/top.v Line: 5
Info (14709): The constrained I/O pad is contained within this pin
Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:15
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error: Quartus Prime Fitter was unsuccessful. 9 errors, 4 warnings
Error: Peak virtual memory: 1342 megabytes
Error: Processing ended: Wed Nov 27 20:03:50 2019
Error: Elapsed time: 00:00:22
Error: Total CPU time (on all processors): 00:00:22
I can change these pins to general GPIO pins and get a successful compilation. Any ideas?
Fomu: usb.out_ev_pending.status: 'CSR' object has no attribute 'status'
litex-boards: 36b7fb1
valentyusb: (hw_cdc_eptri) 371526e432a858b768ddc561cee0d7a0c8f40f42
Hello,
I encountered the following error. Apologies if I made a mistake with setup:
$ ./fomu.py --build
Cloning into 'valentyusb'...
remote: Enumerating objects: 16, done.
remote: Counting objects: 100% (16/16), done.
remote: Compressing objects: 100% (12/12), done.
remote: Total 3056 (delta 5), reused 11 (delta 4), pack-reused 3040
Receiving objects: 100% (3056/3056), 743.77 KiB | 1.08 MiB/s, done.
Resolving deltas: 100% (1980/1980), done.
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-12-20 23:45:50)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : ice40-up5k-uwg30.
INFO:SoC:System clock: 12.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCCSRHandler:cpu CSR allocated at Location 1.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
Traceback (most recent call last):
File "./fomu.py", line 169, in <module>
main()
File "./fomu.py", line 160, in main
**soc_core_argdict(args)
File "./fomu.py", line 93, in __init__
**kwargs)
File "/home/tim/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 181, in __init__
self.add_uart(name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth)
File "/home/tim/timvideos/litex-buildenv/third_party/litex/litex/soc/integration/soc.py", line 1108, in add_uart
self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf)
File "valentyusb/valentyusb/usbcore/cpu/cdc_eptri.py", line 102, in __init__
self.submodules.phy = phy = ClockDomainsRenamer("usb_12")(CDCUsbPHY(iobuf, debug=debug, vid=vid, pid=pid, product=product, manufacturer=manufacturer))
File "valentyusb/valentyusb/usbcore/cpu/cdc_eptri.py", line 461, in __init__
If(usb.out_ev_pending.status,
AttributeError: 'CSR' object has no attribute 'status'
Aller, Nereid, and Tagus targets need updating to new CSR APIs
Trying to build the default Aller target with the latest LiteX and LiteX-boards code results in the following error:
Traceback (most recent call last):
File "./aller.py", line 201, in <module>
main()
File "./aller.py", line 197, in main
soc.generate_software_header("../software/kernel/csr.h")
File "./aller.py", line 182, in generate_software_header
csr_header = get_csr_header(self.get_csr_regions(),
File "/home/dkozel/src/litex/litex/soc/integration/soc_core.py", line 530, in __getattr__
return Module.__getattr__(self, name)
File "/home/dkozel/src/migen/migen/fhdl/module.py", line 136, in __getattr__
raise AttributeError("'"+self.__class__.__name__+"' object has no attribute '"+name+"'")
AttributeError: 'AllerSoC' object has no attribute 'get_csr_regions'
Commit enjoy-digital/litex@8be5824 simplified the handling of csr regions and constants. These target files need to be updated to the new API.
They also still use the with_shadow_base which was removed/deprecated in enjoy-digital/litex@a4ef9b2. I think the new default behavior of get_csr_header is the same as the old behavior with with_shadow_base=False and shadow_base left to the default 0x80000000 value.
However the LitePCIeWishboneBridge from https://github.com/enjoy-digital/litepcie is also using a shadow_base parameter with a value of 0x8000000. The default shadow_base parameter in the LitePCIeWishboneBridge is 0x00000000 so it does need to still be supplied.
https://github.com/enjoy-digital/litepcie/blob/ee78f4f7c0338f6b81e70a2ab5ecc94040d808ba/litepcie/frontend/wishbone.py#L11-L13
So, I think I've fixed both issues correctly in #24 but don't have any hardware to test with. I'm looking at getting an Aller soon and found this while doing a test build.
icebreaker: target features
The icebreaker target was inspired from the Fomu design. I started doing some simplifications with the idea to have something closer to the others targets and just provide a SoC with similar parameters than others SoCs that would run the LiteX BIOS from the SPI Flash. The others SoCs are able to embed the integrated ROM so are not using the SPI Flash for the BIOS so this would provide a good example for this use case.
But, maybe it's not going in the direction you initially wanted @esden, so let's discuss things here, so that i continue or revert my changes :) Are you ok with the direction i'm describing? Do you need specific debug/vexriscv_debug from Fomu in the target or just be able to select the cpu/variant as on others targets is fine?
tinyfpga_bx: vexriscv build error
Build: ./litex-boards/litex_boards/targets/tinyfpga_bx.py --build --cpu-type=vexriscv
Error: ERROR: Unable to place cell 'mem.2.0.0_RAM', no Bels remaining of type 'ICESTORM_RAM'
Full output: https://paste.ubuntu.com/p/wY9rH3bDdT/
serv core builds fine
VCU118: DDR initialization failed
Initializing SDRAM...
SDRAM now under software control
Write leveling:
m0: |11111111111111111111111| delay: 00
m1: |11111111111111111111111| delay: 00
m2: |11111111111111111111111| delay: 00
m3: |11111111111111111111111| delay: 00
m4: |11111111111111111111111| delay: 00
m5: |11111111111111111111111| delay: 00
m6: |11111111111111111111111| delay: 00
m7: |11111111111111111111111| delay: 00
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |11111111111111111111111111111111| delays: 256+-256
best: m0, b7 delays: 256+-256
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |11111111111111111111111111111111| delays: 43+-43
best: m1, b7 delays: 106+-106
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |11110111111101111011111111111111| delays: 08+-08
best: m2, b7 delays: 16+-15
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |00000000000000000000000000000000| delays: -
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |11111111111111111111111111111111| delays: 256+-256
best: m3, b7 delays: 256+-256
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |00000000000000000000000000000000| delays: -
m4, b5: |00000000000000000000000000000000| delays: -
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |11111111111111111111111111111111| delays: 256+-256
best: m4, b7 delays: 256+-256
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00000000000000000000000000000000| delays: -
m5, b5: |00000000000000000000000000000000| delays: -
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |11111111111111111111111111111111| delays: 256+-256
best: m5, b7 delays: 256+-256
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00000000000000000000000000000000| delays: -
m6, b5: |00000000000000000000000000000000| delays: -
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |11111111111111111111111111111111| delays: 256+-256
best: m6, b7 delays: 256+-256
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |00000000000000000000000000000000| delays: -
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: 12+-08
best: m7, b7 delays: 17+-08
SDRAM now under hardware control
Memtest bus failed: 256/256 errors
Memtest data failed: 524288/524288 errors
Memtest addr failed: 8191/8192 errors
Memory initialization failed
Feedback / Contribution / Support
Hackaday Badge : optimize performance
Related to comments in PR #31 (comment)
The performance of the ECP5 Hackaday Badge with 32MB SDRAM is "painfully" slow.
@mithro suggested there could be some issue with the configuration.
@enjoy-digital has attempted some optimizations:
#31 (comment)
With enjoy-digital/litedram@34e6c24 and enjoy-digital/litex@fa22d6a we have a ~10% boot time speedup on designs using SDRAM:
- De0Nano: 94.6.s to 84.6s
- ULX3S: 75.9s to 68.2s
On Arty with DDR3 the gain is effect more limited: 8.7s to 8.4s. That would be interesting to test this on the badge.
I will measure if the boot time improve
quartus constraints are CASE senSitive
("clk25", 0, Pins("AF14"), IOStandard("Differential 1.5V SSTL")),
this yields in constraint being UPPER CASE what causes Quartus to fail, so manual POST generate sdc file patching is needed, then it all works and constraint is recognized
something is weird error comes but not clear why
nexys4ddr - NameError: name 'LiteEthPHYMII' is not defined
0.30s$ ./make.py --board=$BOARD
Traceback (most recent call last):
File "./make.py", line 332, in <module>
main()
File "./make.py", line 283, in main
soc = SoCLinux(board.soc_cls, **soc_kwargs)
File "/home/travis/build/mithro/linux-on-litex-vexriscv/soc_linux.py", line 162, in SoCLinux
return _SoCLinux(**kwargs)
File "/home/travis/build/mithro/linux-on-litex-vexriscv/soc_linux.py", line 55, in __init__
soc_cls.__init__(self, cpu_type="vexriscv", cpu_variant=cpu_variant, uart_baudrate=1e6, **kwargs)
File "/home/travis/build/mithro/linux-on-litex-vexriscv/src/litex-boards/litex_boards/official/targets/nexys4ddr.py", line 82, in __init__
self.submodules.ethphy = LiteEthPHYMII(
NameError: name 'LiteEthPHYMII' is not defined
The command "./make.py --board=$BOARD" exited with 1.
project requires installing dependencies for all platforms/targets
I've recently updated the migen/litex dependencies in a project tree and saw that litex-boards had been split off into it's own repo (yes, I'm slow on the update .. :))
Looking at https://github.com/litex-hub/litex-boards/blob/master/litex_boards/__init__.py , it seems like now litex will try to install dependencies for every possible platform+target, even if it's not actually being used. Or am I just doing something incorrectly? For now I've just locally modified __init__.py to reference only the single target I care about (lattice_versa_ecp5).
ECPIX-5 DDR: Only lower 256MiB pass mem_test
litex> mem_test 0x40000000 0x20000000
Memtest at 0x40000000 (512MiB)...
Write: 0x40000000-0x60000000 512MiB
Read: 0x40000000-0x60000000 512MiB
bus errors: 0/256
addr errors: 0/8192
data errors: 67108864/134217728
Memtest KO
litex> mem_test 0x40000000 0x10000000
Memtest at 0x40000000 (256MiB)...
Write: 0x40000000-0x50000000 256MiB
Read: 0x40000000-0x50000000 256MiB
Memtest OK
The markings on my chip are
OBP47
D9SHG
Looking at micron website this should be 256M x 16 part.
Is there something wrong with my board? Can it be a litex bug?
Colorlight 5A-75B: Connection Timed out by RemoteClient
Hello folks...
Just trying out litex picorv32 etherbone demo code on Colorlight 5a-75b, following the steps mentioned here: dcc65b3#diff-4c555bb99628703ce903d7c79bc090fa
The gateware seems to get jtagged just fine through my FTDI2232 module. I'm getting the LED blink working fine. I'm not sure whether i'm loading the BIOS/picorv32 binaries along with it.
After setting up lxserver --udp, RemoteClient fails to connect to etherbone and says "connection timeout". I tried both Eth ports without luck (please also let me know which physical port is phy0 and which is phy1).
~/exp/cl5a/litex-boards/litex_boards/targets$ ./remote-colorlight_5a_75b.py
Traceback (most recent call last):
File "./remote-colorlight_5a_75b.py", line 21, in <module>
if wb.regs.uart_xover_rxempty.read() == 0:
File "/home/pjp/exp/cl5a/litex/litex/tools/remote/csr_builder.py", line 37, in read
datas = self.readfn(self.addr, length=self.length)
File "/home/pjp/exp/cl5a/litex/litex/tools/litex_client.py", line 49, in read
packet = EtherbonePacket(self.receive_packet(self.socket))
File "/home/pjp/exp/cl5a/litex/litex/tools/remote/etherbone.py", line 365, in receive_packet
chunk = socket.recv(header_length - len(packet))
socket.timeout: timed out
Should i do anything to flash the bios / "software" code separately ?
Partner platforms/target are not modules
litex_boards.partner, litex_boards.partner.platforms and litex_boards.partner.targets are not valid Python modules as they lack __init__.py.
Alveo U280 DDR4 problem
Hello all,
I am working on adding support for the Alveo U280 board (in my case it is ES1) and am using the Alveo U250 platform and target as reference. I was able to generate a minimal SoC and bitstream and boot LiteX, however memory initialization fails. Included below is the boot log including a failing memory test. The board files are at my fork under alveo_u280 branch.
The Alveo U280 is similar to the U250, with a few differences. It has 2 (not 4) DDR4 channels and HBM2. The main clock sources are of 100MHz (not 300MHz). The same MTA18ASF2G72PZ DDR4 module is used. I verified the configuration settings of two identical Vivado MIG+MicroBlaze default designs for the two boards and only the CLK and pins are different.
Any idea what I am doing wrong? Any suggestions are greatly appreciated. Thank you!
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Jan 26 2021 21:29:42
BIOS CRC passed (125b79b6)
Migen git sha1: --------
LiteX git sha1: 737ed9d6
--=============== SoC ==================--
CPU: VexRiscv SMP-LINUX @ 125MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
L2: 0KiB
SDRAM: 1048576KiB 64-bit @ 1000MT/s (CL-9 CWL-9)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
Cmd/Clk scan (0-324)
|000000 |0000 |0000 |0000| best: -1
Setting Cmd/Clk delay to -1 taps.
Data scan:
m0: |1111111111111111111111| delay: -
m1: |1111111111111111111111| delay: -
m2: |1111111111111111111111| delay: -
m3: |1111111111111111111111| delay: -
m4: |1111111111111111111111| delay: -
m5: |1111111111111111111111| delay: -
m6: |1111111111111111111111| delay: -
m7: |1111111111111111111111| delay: -
Write latency calibration:
m0:0 m1:0 m2:0 m3:0 m4:0 m5:0 m6:0 m7:0
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b00 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b00 delays: -
m2, b0: |00000000000000000000000000000000| delays: -
m2, b1: |00000000000000000000000000000000| delays: -
m2, b2: |00000000000000000000000000000000| delays: -
m2, b3: |00000000000000000000000000000000| delays: -
m2, b4: |00000000000000000000000000000000| delays: -
m2, b5: |00000000000000000000000000000000| delays: -
m2, b6: |00000000000000000000000000000000| delays: -
m2, b7: |00000000000000000000000000000000| delays: -
best: m2, b00 delays: -
m3, b0: |00000000000000000000000000000000| delays: -
m3, b1: |00000000000000000000000000000000| delays: -
m3, b2: |00000000000000000000000000000000| delays: -
m3, b3: |00000000000000000000000000000000| delays: -
m3, b4: |00000000000000000000000000000000| delays: -
m3, b5: |00000000000000000000000000000000| delays: -
m3, b6: |00000000000000000000000000000000| delays: -
m3, b7: |00000000000000000000000000000000| delays: -
best: m3, b00 delays: -
m4, b0: |00000000000000000000000000000000| delays: -
m4, b1: |00000000000000000000000000000000| delays: -
m4, b2: |00000000000000000000000000000000| delays: -
m4, b3: |00000000000000000000000000000000| delays: -
m4, b4: |00000000000000000000000000000000| delays: -
m4, b5: |00000000000000000000000000000000| delays: -
m4, b6: |00000000000000000000000000000000| delays: -
m4, b7: |00000000000000000000000000000000| delays: -
best: m4, b00 delays: -
m5, b0: |00000000000000000000000000000000| delays: -
m5, b1: |00000000000000000000000000000000| delays: -
m5, b2: |00000000000000000000000000000000| delays: -
m5, b3: |00000000000000000000000000000000| delays: -
m5, b4: |00000000000000000000000000000000| delays: -
m5, b5: |00000000000000000000000000000000| delays: -
m5, b6: |00000000000000000000000000000000| delays: -
m5, b7: |00000000000000000000000000000000| delays: -
best: m5, b00 delays: -
m6, b0: |00000000000000000000000000000000| delays: -
m6, b1: |00000000000000000000000000000000| delays: -
m6, b2: |00000000000000000000000000000000| delays: -
m6, b3: |00000000000000000000000000000000| delays: -
m6, b4: |00000000000000000000000000000000| delays: -
m6, b5: |00000000000000000000000000000000| delays: -
m6, b6: |00000000000000000000000000000000| delays: -
m6, b7: |00000000000000000000000000000000| delays: -
best: m6, b00 delays: -
m7, b0: |00000000000000000000000000000000| delays: -
m7, b1: |00000000000000000000000000000000| delays: -
m7, b2: |00000000000000000000000000000000| delays: -
m7, b3: |00000000000000000000000000000000| delays: -
m7, b4: |00000000000000000000000000000000| delays: -
m7, b5: |00000000000000000000000000000000| delays: -
m7, b6: |00000000000000000000000000000000| delays: -
m7, b7: |00000000000000000000000000000000| delays: -
best: m7, b00 delays: -
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2MiB)...
Write: 0x40000000-0x40200000 2MiB
Read: 0x40000000-0x40200000 2MiB
bus errors: 256/256
addr errors: 8192/8192
data errors: 524288/524288
Memtest KO
Memory initialization failed
--============= Console ================--
litex> mem_list
Available memory regions:
PLIC 0xf0c00000 0x400000
CLINT 0xf0010000 0x10000
ROM 0x00000000 0x10000
SRAM 0x10000000 0x2000
MAIN_RAM 0x40000000 0x40000000
FIRMWARE_RAM 0x20000000 0x8000
OPENSBI 0x40f00000 0x80000
CSR 0xf0000000 0x10000
litex> mem_test 0x40000000 1024
Memtest at 0x40000000 (1KiB)...
Write: 0x40000000-0x40000400 1KiB
Read: 0x40000000-0x40000400 1KiB
bus errors: 256/256
addr errors: 256/256
data errors: 256/256
Memtest KO
recommended max length for platform/target?
https://github.com/timvideos/litex-buildenv/blob/master/gateware/info/platform.py
there info for platform and target is set to fixed lenght of 8 characters, would it make sense for new targets and plaftorms to keep max_len 8, or is it ok to use longer names?
DDR3 only work at high speed on ZTEX 2.13
Following #164 , the onboard memory of the ZTEX 2.13 works fine at fairly high speed (core @ 90-100 MHz; working was tested with VexRiscV, failing with VexRiscV & Rocket), but fails at lower speed. Initialization simply fails at 100%.
The following magic commands in the BIOS (suggested by @enjoy-digital ) enable the memory to work:
sdram_mr_write 0 2608
sdram_mr_write 1 2054
sdram_mr_write 2 512
sdram_cal
sdram_test
Alternatively, the following patch also solves the problem (same source, tested with Rocket):
diff --git a/litedram/init.py b/litedram/init.py
index d6cc83e..5baaf7e 100644
--- a/litedram/init.py
+++ b/litedram/init.py
@@ -116,7 +116,7 @@ def get_ddr2_phy_init_sequence(phy_settings, timing_settings):
# DDR3 ---------------------------------------------------------------------------------------------
def get_ddr3_phy_init_sequence(phy_settings, timing_settings):
- cl = phy_settings.cl
+ cl = phy_settings.cl + 1
bl = 8
cwl = phy_settings.cwl
Missing TinyFPGA BX target
TinyFPGA BX is listed as a supported open-source board in README, but there are no corresponding script in litex-boards/litex_boards/targets/.
While we do have litex-boards/litex_boards/platforms/tinyfpga_bx.py, I’m not sure if it’s ready to use?
Add QMTech Wukong Board
Hi, All
I had a FPGA board, the chip is Xilinx XC7A100T. The URL is https://github.com/ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD. the board could be found in the following sites.
https://www.aliexpress.com/item/4000170042795.html
http://www.chinaqmtech.com/download_fpga
The below file is what I done until now. it could boot the fpga board, and run into bios.
the qmtech_wukong.platform.txt is been put into platforms, and the qmtech_wukong.target.txt is been put into targets. the output terminal log is wukong.txt.
if open the log file, there is a problem about ddr3 memory initialization. it is failed.
Could any one do me a favor to show me some hint to make the ddr3 memory initialization succeed?
If ddr3 memory initialization succeed, the next step is put linux image into flash, and
run into linux world.
qmtech_wukong.target.txt
qmtech_wukong.platform.txt
wukong.txt
Thanks in advance
BR, Sanada
icebreaker - no BIOS on serial
When I follow the instructions on https://github.com/enjoy-digital/litex (point 4 is missing BTW) I don't get the BIOS output on serial as shown in point 5.
using icebreaker.py --build builds fine without errors, using --load also works fine but does nothing, and using --flash looks like it flashes the icebreaker, but still no serial output. However in that case the board does a slow LED flashing, alternating between green and red LEDs.
I have verified with iceprog that the bios.bin and icebreaker.bin as built match what's in the flash after --flash.
Can you confirm I didn't miss anything? Maybe flesh out point 4 in the docs?
DRAM failed on AC701
Hi, boys and gals. Anyone has any idea why DRAM fails on AC701 boards?
I have two low-end AC701 boards, they all failed on dram test. I tried self-test programs from Xilinx, DRAM seems fine.
I didn't change anything on source code. Built the bitstream using official repo straight away.
--============= Console ================--
litex>
__ _ __ _ __
/ / () /___ | |//
/ /__/ / __/ -)> <
///_/_//|_|
Build your hardware, easily!
(c) Copyright 2012-2020 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 5 2020 17:33:11
BIOS CRC passed (73288079)
Migen git sha1: 7bc4eb1
LiteX git sha1: f7b6dd05
--=============== SoC ==================--
CPU: VexRiscv @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 8-bit data
ROM: 32KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 1048576KiB 64-bit @ 800Mbps/pin
--========== Initialization ============--
Initializing DRAM @0x40000000...
SDRAM now under software control
SDRAM now under software control
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |00000000000000000000000000000000| delays: -
m0, b03: |00000000000000000000000000000000| delays: -
m0, b04: |00000000000000000000000000000000| delays: -
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
m0, b08: |00000000000000000000000000000000| delays: -
m0, b09: |00111111111110000000000000000000| delays: 07+-05
m0, b10: |00000000000000000011111111111000| delays: 23+-05
m0, b11: |00000000000000000000000000000000| delays: -
m0, b12: |00000000000000000000000000000000| delays: -
m0, b13: |00000000000000000000000000000000| delays: -
m0, b14: |00000000000000000000000000000000| delays: -
m0, b15: |00000000000000000000000000000000| delays: -
best: m0, b09 delays: 07+-05
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |00000000000000000000000000000000| delays: -
m1, b03: |00000000000000000000000000000000| delays: -
m1, b04: |00000000000000000000000000000000| delays: -
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
m1, b08: |00000000000000000000000000000000| delays: -
m1, b09: |01111111111110000000000000000000| delays: 07+-06
m1, b10: |00000000000000000111111111111000| delays: 23+-06
m1, b11: |00000000000000000000000000000000| delays: -
m1, b12: |00000000000000000000000000000000| delays: -
m1, b13: |00000000000000000000000000000000| delays: -
m1, b14: |00000000000000000000000000000000| delays: -
m1, b15: |00000000000000000000000000000000| delays: -
best: m1, b09 delays: 07+-06
m2, b00: |00000000000000000000000000000000| delays: -
m2, b01: |00000000000000000000000000000000| delays: -
m2, b02: |00000000000000000000000000000000| delays: -
m2, b03: |00000000000000000000000000000000| delays: -
m2, b04: |00000000000000000000000000000000| delays: -
m2, b05: |00000000000000000000000000000000| delays: -
m2, b06: |00000000000000000000000000000000| delays: -
m2, b07: |00000000000000000000000000000000| delays: -
m2, b08: |00000000000000000000000000000000| delays: -
m2, b09: |00000000000000000000000000000000| delays: -
m2, b10: |00000000000000000000000000000000| delays: -
m2, b11: |00000000000000000000000000000000| delays: -
m2, b12: |00000000000000000000000000000000| delays: -
m2, b13: |00000000000000000000000000000000| delays: -
m2, b14: |00000000000000000000000000000000| delays: -
m2, b15: |00000000000000000000000000000000| delays: -
best: m2, b00 delays: -
m3, b00: |00000000000000000000000000000000| delays: -
m3, b01: |00000000000000000000000000000000| delays: -
m3, b02: |00000000000000000000000000000000| delays: -
m3, b03: |00000000000000000000000000000000| delays: -
m3, b04: |00000000000000000000000000000000| delays: -
m3, b05: |00000000000000000000000000000000| delays: -
m3, b06: |00000000000000000000000000000000| delays: -
m3, b07: |00000000000000000000000000000000| delays: -
m3, b08: |00000000000000000000000000000000| delays: -
m3, b09: |00000000000000000000000000000000| delays: -
m3, b10: |00000000000000000000000000000000| delays: -
m3, b11: |00000000000000000000000000000000| delays: -
m3, b12: |00000000000000000000000000000000| delays: -
m3, b13: |00000000000000000000000000000000| delays: -
m3, b14: |00000000000000000000000000000000| delays: -
m3, b15: |00000000000000000000000000000000| delays: -
best: m3, b00 delays: -
m4, b00: |00000000000000000000000000000000| delays: -
m4, b01: |00000000000000000000000000000000| delays: -
m4, b02: |00000000000000000000000000000000| delays: -
m4, b03: |00000000000000000000000000000000| delays: -
m4, b04: |00000000000000000000000000000000| delays: -
m4, b05: |00000000000000000000000000000000| delays: -
m4, b06: |00000000000000000000000000000000| delays: -
m4, b07: |00000000000000000000000000000000| delays: -
m4, b08: |00000000000000000000000000000000| delays: -
m4, b09: |00000000000000000000000000000000| delays: -
m4, b10: |00000000000000000000000000000000| delays: -
m4, b11: |00000000000000000000000000000000| delays: -
m4, b12: |00000000000000000000000000000000| delays: -
m4, b13: |00000000000000000000000000000000| delays: -
m4, b14: |00000000000000000000000000000000| delays: -
m4, b15: |00000000000000000000000000000000| delays: -
best: m4, b00 delays: -
m5, b00: |00000000000000000000000000000000| delays: -
m5, b01: |00000000000000000000000000000000| delays: -
m5, b02: |00000000000000000000000000000000| delays: -
m5, b03: |00000000000000000000000000000000| delays: -
m5, b04: |00000000000000000000000000000000| delays: -
m5, b05: |00000000000000000000000000000000| delays: -
m5, b06: |00000000000000000000000000000000| delays: -
m5, b07: |00000000000000000000000000000000| delays: -
m5, b08: |00000000000000000000000000000000| delays: -
m5, b09: |00000000000000000000000000000000| delays: -
m5, b10: |00000000000000000000000000000000| delays: -
m5, b11: |00000000000000000000000000000000| delays: -
m5, b12: |00000000000000000000000000000000| delays: -
m5, b13: |00000000000000000000000000000000| delays: -
m5, b14: |00000000000000000000000000000000| delays: -
m5, b15: |00000000000000000000000000000000| delays: -
best: m5, b00 delays: -
m6, b00: |00000000000000000000000000000000| delays: -
m6, b01: |00000000000000000000000000000000| delays: -
m6, b02: |00000000000000000000000000000000| delays: -
m6, b03: |00000000000000000000000000000000| delays: -
m6, b04: |00000000000000000000000000000000| delays: -
m6, b05: |00000000000000000000000000000000| delays: -
m6, b06: |00000000000000000000000000000000| delays: -
m6, b07: |00000000000000000000000000000000| delays: -
m6, b08: |00000000000000000000000000000000| delays: -
m6, b09: |00000000000000000000000000000000| delays: -
m6, b10: |00000000000000000000000000000000| delays: -
m6, b11: |00000000000000000000000000000000| delays: -
m6, b12: |00000000000000000000000000000000| delays: -
m6, b13: |00000000000000000000000000000000| delays: -
m6, b14: |00000000000000000000000000000000| delays: -
m6, b15: |00000000000000000000000000000000| delays: -
best: m6, b00 delays: -
m7, b00: |00000000000000000000000000000000| delays: -
m7, b01: |00000000000000000000000000000000| delays: -
m7, b02: |00000000000000000000000000000000| delays: -
m7, b03: |00000000000000000000000000000000| delays: -
m7, b04: |00000000000000000000000000000000| delays: -
m7, b05: |00000000000000000000000000000000| delays: -
m7, b06: |00000000000000000000000000000000| delays: -
m7, b07: |00000000000000000000000000000000| delays: -
m7, b08: |00000000000000000000000000000000| delays: -
m7, b09: |00000000000000000000000000000000| delays: -
m7, b10: |00000000000000000000000000000000| delays: -
m7, b11: |00000000000000000000000000000000| delays: -
m7, b12: |00000000000000000000000000000000| delays: -
m7, b13: |00000000000000000000000000000000| delays: -
m7, b14: |00000000000000000000000000000000| delays: -
m7, b15: |00000000000000000000000000000000| delays: -
best: m7, b00 delays: -
SDRAM now under hardware control
Memtest at 0x40000000...
[########################################]
[########################################]
- bus errors: 256/256
- addr errors: 4095/8192
- data errors: 524285/524288
Memtest KO
Memory initialization failed
--============= Console ================--
`./orangecrab.py --revision r0.1 --device 85F` generates code for a 25F device
Following the directions from https://github.com/enjoy-digital/litex/blob/master/README.md and executing the target ./orangecrab.py --revision r0.1 --device 85F resulted in a
./soc_basesoc_orangecrab/gateware/build_top.sh with
# Autogenerated by LiteX / git: 34f26868
set -e
yosys -l top.rpt top.ys
nextpnr-ecp5 --json top.json --lpf top.lpf --textcfg top.config --25k --package CSFBGA285 --speed 8 --timing-allow-fail
ecppack top.config --svf top.svf --bit top.bit
The --25k should be --85k
When fixing this manually the result builds and runs, but SDRAM test fails, so I suspect the revision also isn't propagated correctly.
Custom Zynq board
I am trying to develop a custom zynq board. Can anyone point to how I can generate this xci file that the zybo target uses?
ModuleNotFoundError: No module named 'litex_boards'
import litex_boards triggers a ModuleNotFoundError: No module named 'litex_boards'. This is due to setup.py not registering packages in setuptools.setup().
ulx3s.py bitstream fails LiteX memory test (memory otherwise ok)
the ulx3s.py is now failing memory test:
$ $WORKSPACE/ulx3s-examples/bin/ujprog.exe top.bit
ULX2S / ULX3S JTAG programmer v 3.0.92 (built Feb 18 2019 10:55:47)
Using USB cable: ULX3S FPGA 12K v3.0.3
Programming: 100%
Completed in 63.63 seconds.
gojimmypi:/mnt/c/workspace/litex-boards/litex_boards/targets/soc_basesoc_ulx3s/gateware
$ litex_term --serial-boot --kernel bios.bin /dev/ttyS15
[LXTERM] Starting....
litex> memtest
Memtest bus failed: 30/256 errors
Memtest data failed: 48626/524288 errors
Memtest addr failed: 594/8192 errors
my standard build is here, but I've also tried a more explicit match of RAM chip that I have with the same results:
./ulx3s.py --sdram-module AS4C32M16 --device LFE5U-85F --cpu-type picorv32
I've run emard's memtest, specifically the ulx3s_85f_memtest_32MB_190MHz_300deg.bit and confirmed memory seems ok.
(top row yellow not used; next row: numbers of tests; bottom row: errors)
is this a known problem or perhaps I am doing something wrong here? I had this working not long ago.
*edit: the problem seems to be in the toolchain, and not the ULX3S.py file. I updated everything today with ./litex_setup.py init --user and ./litex_setup.py install --user as noted in enjoy-digital/litex#463 (comment)
Note that I had this working on 3/22:
yet git checkout master@{3/22/2020} in this repo, and I still see a memtest failure.
There are a bunch of warnings:
4.56. Executing CHECK pass (checking for obvious problems).
checking module top..
Warning: Wire top.builder_array_muxed0 has an unprocessed 'init' attribute.
Warning: Wire top.builder_array_muxed1 has an unprocessed 'init' attribute.
Warning: Wire top.builder_array_muxed2 has an unprocessed 'init' attribute.
[...snip...]
Warning: Wire top.main_sdram_bankmachine0_auto_precharge has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_a has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_cas has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_is_cmd has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_is_read has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_is_write has an unprocessed 'init' attribute.
Warning: Wire top.main_sdram_bankmachine0_cmd_payload_ras has an unprocessed 'init' attribute.
[...snip... many more similar main_sdram warnings ]
since it worked before, I did actually go back and look at the prior logs. So I don't know if this is a new and important warning or not.
about add QMTech Wukong Board
Hi, All
I had a FPGA board, the chip is Xilinx XC7A100T. The URL is https://github.com/ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD. the board could be found in the following sites.
https://www.aliexpress.com/item/4000170042795.html
http://www.chinaqmtech.com/download_fpga
after some study on how to add this board into litex-boards project, the current result is the attached files. but I got some errors. Does anyone could do me a favor to show me how to get rid of this errors. If you want to try what I made, you could download the files, and following the below instruction.
move make.txt to make.py
move qmtech_wukong.platform.txt to litex_boards/platforms/qmtech_wukong.py
move qmtech_wukong.target.txt to litex_boards/targets/qmtech_wukong.py
The first problem is about clock input pin. in the schematic, the fpga's clock is in M22.
the output message's meaning is due to M22 is N-side pin, and couldn't be used as clock input.
the second problem is about DDR3 memory. the DDR3 memory chip is as the same as ARTY-A7.
as a good reference, and reassign the pin, the DDR3 memory setting is done. But during building phase, the error message shows up the reference voltage of the bank 16 to DDR3 pins is 1.35V. after some trying, by adding [litex_boards/platforms/qmtech_wukong.py] in targets setting file, the error seems gone. but I'm not sure this is the right way or not.
make.txt
qmtech_wukong.platform.txt
qmtech_wukong.target.txt
Many Thanks.
BR, Sanada
hadbadge: make.py build: ValueError (Invalid speed grade c)
@enjoy-digital I am creating a new issue rather than continuing to comment on the closed PR:
#31 (comment)
I still get this error during build for the hadbadge:
pdp7@x1:~/dev/upstream/linux-on-litex-vexriscv$ python3 make.py --board=hadbadge --build
make: Entering directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libcompiler_rt'
make: Entering directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
CC exception.o
CC system.o
CC id.o
CC uart.o
CC time.o
CC spiflash.o
CC mdio.o
AR libbase.a
AR libbase-nofloat.a
make: Leaving directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libbase'
make: Entering directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
CC microudp.o
AR libnet.a
make: Leaving directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/libnet'
make: Entering directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/bios'
CC isr.o
CC sdram.o
/home/pdp7/dev/upstream/litex/litex/soc/software/bios/sdram.c: In function 'sdrrderr':
/home/pdp7/dev/upstream/litex/litex/soc/software/bios/sdram.c:225:49: warning: division by zero [-Wdiv-by-zero]
printf("%2x", DFII_PIX_DATA_BYTES/2 - 1 - (i % (DFII_PIX_DATA_BYTES/2)));
^
CC main.o
CC boot.o
LD bios.elf
chmod -x bios.elf
OBJCOPY bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
make: Leaving directory '/home/pdp7/dev/upstream/linux-on-litex-vexriscv/build/hadbadge/software/bios'
Traceback (most recent call last):
File "make.py", line 318, in <module>
main()
File "make.py", line 305, in main
builder.build()
File "/home/pdp7/dev/upstream/litex/litex/soc/integration/builder.py", line 182, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/pdp7/dev/upstream/litex/litex/soc/integration/soc_core.py", line 461, in build
return self.platform.build(self, *args, **kwargs)
File "/home/pdp7/dev/upstream/litex/litex/build/lattice/platform.py", line 34, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/pdp7/dev/upstream/litex/litex/build/lattice/trellis.py", line 213, in build
(family, size, speed_grade, package) = nextpnr_ecp5_parse_device(platform.device)
File "/home/pdp7/dev/upstream/litex/litex/build/lattice/trellis.py", line 83, in nextpnr_ecp5_parse_device
raise ValueError("Invalid speed grade {}".format(speed_grade))
ValueError: Invalid speed grade c
Mercury XU5: DDR initialization failed
The write leveling succeeds but read leveling fails:
--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Write leveling:
m0: |000000001111111111111| delay: 127
m1: |000000000111111111111| delay: 131
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000000000000000000000000000000| delays: -
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b0 delays: -
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |00000000000000000000000000000000| delays: -
m1, b6: |00000000000000000000000000000000| delays: -
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b0 delays: -
SDRAM now under hardware control
Memtest bus failed: 128/256 errors
Memtest data failed: 524288/524288 errors
Memtest addr failed: 8192/8192 errors
Memory initialization failed
--============= Console ================--
litex>
Mercury XU5: memory initialization fails at 125 MHz
When working on enjoy-digital/litex#472 I had to decrease the sys_clk_freq because at frequency of 125 MHz the memory initialization fails. The highest working frequency I could get was 120 MHz (with 480 MHz for IDELAYCTRL).
It looks as if, for higher frequency, clock/command delay has much bigger influence than DQ/DQS delay, e.g.
litex> sdram_cdly 27
Write leveling:
M0: |00000000000000000000000| delay: -1
M1: |00000000000000000000000| delay: -1
litex> sdram_cdly 28
Write leveling:
M0: |11111111111111111111111| delay: -1
M1: |00000000000000000000000| delay: -1
litex> sdram_cdly 29
Write leveling:
M0: |11111111111111111111111| delay: -1
M1: |00000000000000000000000| delay: -1
litex> sdram_cdly 30
Write leveling:
M0: |11111111111111111111111| delay: -1
M1: |00000000000000000000000| delay: 197
litex> sdram_cdly 31
Write leveling:
M0: |11111111111111111111111| delay: -1
M1: |11111111111111111111111| delay: -1
Sometimes (as here for cdly 30) a single scan can be different than the rest. But when I added printing the number of the 1s registered, it was always either 0/128 or 128/128, so all the loops for a given delay were giving the same result. It looks like the problem is in incrementing the write delay, but inserting additional delays in software didn't help.
Add Tiny FPGA EX support
- Verify ECP5 diamond build support.
- Verify programmer support.
- Add platform.
- Add target with BaseSoC.
- Integrate HyperRam to target core:
https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/hyperbus.py
Use LCD on hadbadge from Linux
@gregdavill
I am using:
https://github.com/gregdavill/litevideo/tree/terminal-readback
https://github.com/gregdavill/linux-on-litex-vexriscv/tree/hadbadge-flash
I am getting error:
File "/home/pdp7/dev/enjoy/greg-linux-on-litex-vexriscv/soc_linux.py", line 218, in add_framebuffer
from dma import StreamReader, StreamWriter
ModuleNotFoundError: No module named 'dma'
https://gist.github.com/pdp7/c3c735969bb7264cb4435bbb8510e365
Am I missing something? Thanks
ecpix-5 target sys clk frequency seems wrong 75MHz instead of 100MHz
It seems https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/ecpix5.py sys_clk_freq is wrong it shall be set to 100MHz instead of 75MHz thanks to clarify that (why it is changed to 75MHz instead of using native input clock of 100MHz)
See also #138
Generated C code fails to compile when no uart is enabled
For example in the sds1104xe board, which has no uart,
the generated code fails to compile, because still
some IRQ related code is generated, but without the
definitions in the header.
This issue also is relevant for other boards,
when uart is being disabled.
boot hadbadge from flash
While the kernel boots in under 30 seconds, it currently it takes about 2 minutes to load the kernel Image and rootfs.cpio:
lxterm --images=images.json /dev/ttyUSB0 --speed=1e6 --no-crc
The badge and cartridge both have:
I want to use the built-in Flash to store the kernel and rootfs rather than load over serial.
I initially was discussing this in #35 but I wanted to start a new issue to decouple this effort from the memory access optimization that @enjoy-digital already completed in enjoy-digital/litedram@721c84b and enjoy-digital/litex@39ce39a
ZCU104: get ddram_64 working
Following the discussion in #47.
Currently, only ddram_32 is working. The read leveling is not working correctly on the first 4 modules when using ddram_64.
kc705.py doesn't build with cpu-type set to None
@enjoy-digital Looks like this 9d1443c1 in Litex repo
:~/software/litex/litex-boards/litex_boards/targets$ master$ python kc705.py --with-ethernet --cpu-type None
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2020-07-12 13:30:09)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7k325t-ffg900-2.
INFO:SoC:System clock: 125.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:8-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCBusHandler:io0 Region added at Origin: 0x00000000, Size: 0x100000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x01000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:uart_phy CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 4.
ERROR:SoCBusHandler:Region overlap between rom and csr:
ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
ERROR:SoCBusHandler:Origin: 0x00000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Traceback (most recent call last):
File "kc705.py", line 113, in <module>
main()
File "kc705.py", line 104, in main
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
File "kc705.py", line 55, in __init__
**kwargs)
File "/home/w/software/litex/litex/litex/soc/integration/soc_core.py", line 187, in __init__
self.add_csr_bridge(self.mem_map["csr"])
File "/home/w/software/litex/litex/litex/soc/integration/soc.py", line 752, in add_csr_bridge
self.bus.add_slave("csr", self.csr_bridge.wishbone, csr_region)
File "/home/w/software/litex/litex/litex/soc/integration/soc.py", line 333, in add_slave
self.add_region(name, region)
File "/home/w/software/litex/litex/litex/soc/integration/soc.py", line 207, in add_region
raise
RuntimeError: No active exception to reraise
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