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limesdr-usb_gw's Introduction

LimeSDR-USB FPGA gateware

This repository contains the FPGA gateware project for the USB 3.0 LimeSDR board.

The gateware can be built with the free version of the Altera Quartus tools.

Branches

This repository contains the following hardware-specific branches:

  • master:

    • Compiled gateware file for Hardware Revision 1v4 is output_files/LimeSDR-USB_lms7_trx_HW_1.4.rbf.
  • HW_v1.3-v1.0:

    • Compiled gateware file for Hardware Revision 1v3 is output_files/LimeSDR-USB_lms7_trx_HW_1.3.rbf.
    • Compiled gateware file for Hardware Revision 1v2 is output_files/LimeSDR-USB_lms7_trx_HW_1.2.rbf.
    • Compiled gateware file for Hardware Revision 1v1 is output_files/LimeSDR-USB_lms7_trx_HW_1.1.rbf.
    • Compiled gateware file for Hardware Revision 1v0 is output_files/LimeSDR-USB_lms7_trx_HW_1.0.rbf.

Licensing

Please see the COPYING file(s). However, please note that the license terms stated do not extend to any files provided with the Altera design tools and see the relevant files for the associated terms and conditions.

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limesdr-usb_gw's Issues

Help with modifying the FPGA for custom use

Hello,

I've cloned the repo and been trying to get my head around the FPGA part trying to figure which parts are relevant to me, but it's being quite challenging.

I'm trying to listen to a wide RF band and, using FIR filters and a selector, send a few of the highest power channels for processing using GNUradio.

So basically, I'm looking for ways to get the signal from RX (I only need one antenna), and to send the processed signals to the computer.
In short, what I'm looking for is the signal from RX, and where to send my altered signal for it to be sent to USB.

If possible, I'd like to keep using the osmocom source with the Soapy drivers, so maintaining compatibility with how data is sent normally would be a plus. Is there something I have to take into account before multiplexing my signal ?
It seems the bitrate for a signal is 24 times its sample rate, that would suggest that two 12bits ADC samples are used to make one Complex sample in GNU Radio. Should my multiplexing look like mux(a,b)=[(a[i], a[i+1], b[i], b[i+1]) for i in [0:end:2]], which the GNU Radio SDR source block should convert to a complex signal where a and b samples are alternated as [a,b,a,b...], decimating the signal with step=2 ? Or am I mistaken ?

Thanks in advance for any help you would take the time to provide.

TX streaming fails with version 18.06

The latest version of LimeSuite + FPGA GW + FX3 FW doesn't work for me in TX (RX works perfectly). For easy testing, I'm using the following Python script that uses SoapySDR to send samples to the LimeSDR-USB for TX.

#!/usr/bin/env python2

import SoapySDR
from SoapySDR import * #SOAPY_SDR_ constants
import numpy as np

sdr = SoapySDR.Device()

#apply settings
sdr.setSampleRate(SOAPY_SDR_TX, 0, 1e6)
sdr.setFrequency(SOAPY_SDR_TX, 0, 434e6)
sdr.setAntenna(SOAPY_SDR_TX, 0, 'BAND1')

#setup a stream (complex floats)
txStream = sdr.setupStream(SOAPY_SDR_TX, SOAPY_SDR_CF32, [0])
sdr.activateStream(txStream) #start streaming

#create a re-usable buffer for rx samples
N = 2**18
N = 1024
buff = np.zeros(N, dtype=np.complex64)
while True:
    sr = sdr.writeStream(txStream, [buff], N)
    print sr

The script starts running fine and we get

ret=1024, flags=0, timeNs=0

but after a very small time we start getting

ret=-1, flags=0, timeNs=0

for all calls to writeStream().

Other SDR softwares fail as well. For instance, when using GNU Radio through gr-osmosdr or through gr-limesdr, the LimeSDR sink quickly blocks and doesn't accept any new samples.

Testing combinations of older versions of LimeSuite, the FPGA GW and the FX3 FW I have determined the culprit to be version 18.06 of the FPGA GW (LimeSDR-USB_HW_1.4_r2.15.rbf). When downgrading the FPGA GW and FX3 FW to version 18.03, everything works fine, even with the master branch of LimeSuite. Also, everything works fine if I mix FPGA GW version 18.03 with FX3 FW version 18.06. I guess that the problem must be in FPGA GW version 18.06.

fx3_led_ctrl.vhd

I had to change the file name to FX3_LED_ctrl.vhd before I could get a compile

Quartus 18.1 does not have DDR2 IPCore

Hello
i try to compile on quatus 18.1 but could not find DDR2 ip core now DDR2 altmemphy supporting
please help us how can we compile on Quartus 18.1
Thanks
Nome

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