prasadp4009 / tbengy Goto Github PK

It would be great to support the open source FPGA tooling from https://f4pga.org/ project. Examples on how to use the tooling for Xilinx 7 series parts can be found here -> https://f4pga-examples.readthedocs.io/en/latest/building-examples.html#xilinx-7-series

There are prebuilt binaries distributed through conda available at https://github.com/hdl/conda-hdl including SystemVerilog support using the Surelog->UHDM->Yosys tooling.

FYI - Xilinx has also published an open source version of the UniSim library @ https://github.com/Xilinx/XilinxUnisimLibrary

Hi all,

I created this enhancement request to update UVM template example. The current one is simple ram, but is not easily synthesizable on FPGA to visually verify on board. I am open to suggestions. Following are simple examples I am looking at

(As most Boards contain atleast 4 easily addresable LEDs, I plan to add that)

• 4 bit Up counter with output on LEDs
• Pattern Generator with output on LEDs
• Pattern Checker with output on LEDs

The examples should be portable on all boards considering feature availability and should be complex enough to write tests in UVM.