qshen3 / cnn-fpga Goto Github PK
View Code? Open in Web Editor NEW使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
License: MIT License
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CNN-FPGA
你好，请问我在哪里能查找到你的毕业论文呢？我希望能够拜读你的论文以获取更多思路。谢谢！
仿真无法通过
作者你好，我在运行你的代码后，联合modelsim仿真报错Illegal output port connection for 'result' (2nd connection) to reg type. 在将Max_pool文件中的result更改为wire后，报错CNN-FPGA-master/src/Conv2d.v(117): (vopt-2957) MSB of part-select into 'result' is out of bounds.请问你在仿真时可以通过么？这个问题可能是出在哪里呢？烦请指教，感谢！
卷积层结果尺寸
在PADDINGENABLE == 0 时，卷积层结果尺寸应该是
(DATAWIDTH - FILTERWIDTH ) / STRIDEWIDTH + 1
而Conv2d模块里使用的是
(DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH
感觉这里存在问题，如果说得不对，请指正，谢谢
输入图像
您好，我想问一下输入data 是从哪里来的
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