secworks / aes Goto Github PK

FYI, Lubis (@ludwigatlubis) is doing FPV to verify the AES right now and they found a bug according to the NIST specification.

Module that contains the bug:
src/rtl/aes_decipher_block.v

The bug is in line 326 invs_shift_rows_block() function should not get executed in the init_update state, as it is repeated in the next state again.

Reproduce the bug:
A simple formal assertion shows the bug.

Solution:
Removing that line fixes the bug.

We are working on it here: chipsalliance/caliptra-rtl#165

Hello,
May you upload schematic block diagram of the module?
Thank you very much!

May I know where to input text file in this series of Verilog codes?
Thank you.

It seems the edalize based CI build for skywater is broken (again):

`Error: : during executing openroad script /openlane/scripts/openroad/groute.tcl
Error: : Exit code: 1
Error: : Last 10 lines:

ERROR: Unable to find image 'edalize/openlane-sky130:mpw4' locally

...
...

Status: Downloaded newer image for edalize/openlane-sky130:mpw4
no such variable
(read trace on "::env(PWD)")
invoked from within
"relpath $::env(PWD) $reproducible_dir"
(procedure "run_openroad_script" line 38)
invoked from within
"run_openroad_script $::env(SCRIPTS_DIR)/openroad/groute.tcl -indexed_log $saveLOG"
(procedure "global_routing_fastroute" line 5)
invoked from within
"global_routing_fastroute"
(procedure "global_routing" line 13)
invoked from within
"global_routing"
(procedure "run_routing" line 35)
invoked from within
"run_routing"
(procedure "run_routing_step" line 7)
invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
(procedure "run_non_interactive_mode" line 54)
invoked from within
"run_non_interactive_mode {*}$argv"
invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
puts_info "Running interactively"
if { [info exists arg_values(-file)..."
(file "/openlane/flow.tcl" line 346)
make: *** [Makefile:4: all] Error 1

ERROR: Failed to build secworks:crypto:aes:0 : '['make']' exited with an error: 2

Error: Process completed with exit code 1.
`

Any idea what the error is @olofk ?

Sir, the test bench file has errors. Can you please send the updated file?

Hi,
is it possible to use aes_encipher_block for exactly one AES round like the AES-NI instruction __m128i _mm_aesenc_si128(__m128i a, __m128i RoundKey)? [Link]
If I have to update a few lines in the component this would be totally fine.

From the documentation of the AES-NI instruction _mm_aesenc_si128:

state := a
a[127:0] := ShiftRows(a[127:0])
a[127:0] := SubBytes(a[127:0])
a[127:0] := MixColumns(a[127:0])
dst[127:0] := a[127:0] XOR RoundKey[127:0]

The encipher component does exactly that, but also does the initial round key addition and the final round (without mixing). Is there a way to avoid the initial key addition? I tried to modify the code in this line so the round key does not get xor'd to the block, but it didn't get me the expected result. Is there something else I could do/might try?

Here is an example of a software AES-NI that I use to generate my expected values. [Link]. You can also see the expected values it produces as a comment in the gist.

After the first round (without key addition) with the following parameters:
block = 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f and
round_key = 06 84 70 4c e6 20 c0 0a b2 c5 fe f0 75 81 7b 9d
keylen = 0
I expect new_block to be: f7 11 dd 30 dc 93 f6 e3 ba 19 7d 87 6b ec a5 5a

The goal of all this is to use the aes_encipher_block component for a hardware implementation of Haraka.

Hi, I am very new here, and I am still very confused here after reviewing the AES core. I am not sure if the key is stored in one of local parameters on the AES core, or it is stored outside the AES core.
If the key is stored beyond the core, I donot know how to load it to the core according to the port definition on the top file. It is just write_data/read_data for encrypted/decrypted data, and address for registers.

Add a simple description of how the core is to be used to the README.md
Something like:
1. Load the key to be used by writing to the key register words.
2. Set the key length by writing to the config register.
3. Initialize key expansion by writing a one to the init bit in the control register.
4. Wait for the ready bit in the status register to be cleared and then to be set again. This means that the key expansion has been completed.
5. Write the cleartext block to the block registers.
6. Start block processing by writing a one to the next bit in the control register.
7. Wait for the ready bit in the status register to be cleared and then to be set again. This means that the data block has been processed.
8. Read out the ciphertext block from the result registers.