Topic: asic-design Goto Github
Some thing interesting about asic-design
Some thing interesting about asic-design
asic-design,I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
User: abdelazeem201
asic-design,The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
User: abdelazeem201
asic-design,Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
User: abdelazeem201
asic-design,IC implementation of Systolic Array for TPU
User: abdelazeem201
asic-design,Design & Implementation of Multi Clock Domain System using Verilog HDL
User: ahmedamrabdellatif1
asic-design,A simple Recap for different Digital Design topics from different references and books.
User: amrmeid
asic-design,Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
User: andrsmllr
asic-design,Blockdiagramm is a graphical block design tool for IC design
User: aperture-electronic
asic-design,This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
User: arhamhashmi01
asic-design,Standard Cell Library based Memory Compiler using FF/Latch cells
Organization: aucohl
asic-design,A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
User: boooc
asic-design,VeeR EH1 core
Organization: chipsalliance
asic-design,VeeR EL2 Core
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/Cores-VeeR-EL2/html/
asic-design,Open Application-Specific Instruction Set processor tools (OpenASIP)
Organization: cpc
Home Page: http://openasip.org
asic-design,Moore.io Demo Project
Organization: datum-technology-corporation
Home Page: https://www.mooreio.com/
asic-design,A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
User: dpretet
asic-design,An AXI4 crossbar implementation in SystemVerilog
User: dpretet
asic-design,Implementation of a binary search tree algorithm in a FPGA/ASIC IP
User: dpretet
asic-design,E&D Skill Application Manager (SAM)
Organization: electronics-and-drives
asic-design,SKILL Package Manager
Organization: electronics-and-drives
asic-design,Blake2 RTL implementation
User: essenceia
Home Page: https://essenceia.github.io/projects/blake2/
asic-design,QKeras: a quantization deep learning library for Tensorflow Keras
Organization: google
asic-design,OpenSource GPU, in Verilog, loosely based on RISC-V ISA
User: hughperkins
asic-design,A place to keep my synthesizable verilog examples.
User: jeffdecola
asic-design,An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Organization: kastnerrg
asic-design,Quasar 2.0: Chisel equivalent of SweRV-EL2
Organization: lampro-mellon
asic-design,KiCad symbol library for sky130 and gf180mcu PDKs
User: lethalbit
asic-design,Convolutional accelerator kernel, target ASIC & FPGA
User: lirui-shanghaitech
asic-design,Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
User: luca-dalmasso
asic-design,300 baud 8N1 UART transmitter with limited character set (0x40..0x5F) loading as ASIC design
User: maehw
asic-design,
User: meeeeet
asic-design,MATLAB code for the lab sessions in the "ASIC for DSP" course at LiU-ISY
User: mnemocron
Home Page: https://www.isy.liu.se/en/edu/kurs/TSTE87/laboration/
asic-design,PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.
User: mostafa-elgendy22
asic-design,This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
User: neeraj1397
asic-design,developing a Game on Fpga using VHDL
User: omaraskour
asic-design,"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
User: orsuvenkatakrishnaiah1235
asic-design,High-Performance Binary Neural Networks for MNIST Classification: From Software to ASIC
User: prithvish04
asic-design,Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
User: rubinsteina13
Home Page: https://en.wikipedia.org/wiki/Alpha%E2%80%93beta_transformation
asic-design,Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
User: rubinsteina13
Home Page: https://www.xilinx.com/support/documentation/application_notes/xapp154.pdf
asic-design,Synthesizable SystemVerilog IP-Core of the I2S Receiver
User: rubinsteina13
asic-design,The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
User: sinakarvandi
Home Page: https://rayanfam.com/topics/hardware-design-stack/
asic-design,CPEN 211: Introduction to Microcomputers 2022W1 with Prof. Lis
User: skipfie
asic-design,🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
User: stnolting
asic-design,hardware design of universal NPU(CNN accelerator) for various convolution neural network
User: thousrm
asic-design,This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
User: vardhansuroshi
asic-design,Implementation (VHDL) and verification of the accelerator proposed in the paper "Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification", from May 2020
User: vctrop
asic-design,TCL Script automating the frontend of ASIC design
User: visruat
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