Topic: vlsi-design Goto Github
Some thing interesting about vlsi-design
Some thing interesting about vlsi-design
vlsi-design,This is the Repository which contains the detail of my work done at SCL Mohali (formerly Department of Space, ISRO). This was the internship basically focused on the "Experimental Analysis of MOS Capacitor for Oxide Furnaces" and further study of VLSI.
User: adarshmishra26
Home Page: https://sclinternship26.vercel.app
vlsi-design,This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
User: ads930
vlsi-design,ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
User: aesthet1c0der
vlsi-design,Cmos design of 16 bit adder 8bit full adder + 8 bit cla adder
User: ahmetdenizyilmaz
vlsi-design,Study Of Static CMOS Inverter
User: aroondhati
vlsi-design,Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
User: chrisshakkour
vlsi-design,"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
User: ekb0412
vlsi-design,We are designing a CP-PLL. The following link provides resources about PLL design.
Organization: electro-spy
Home Page: https://drive.google.com/drive/folders/1gMaTpMKlD9F_9fX-aojiaM1V_fqbmQ_w?usp=sharing
vlsi-design,This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments
User: harsh-kmr
vlsi-design,Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
User: hibagus
vlsi-design,VLSI Design - Spring 2022
User: iamraufu
vlsi-design,A simple tool to demonstrate the physical design steps of VLSI Design Flow.
User: karthik-r-rao
vlsi-design,This is part of EC383 - Mini Project in VLSI Design.
User: krutideepanpanda
vlsi-design,Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
Organization: lip6
Home Page: https://coriolis.lip6.fr
vlsi-design,The Repository contains the code of various Digital Circuits
User: maazm007
vlsi-design,This is a basic project of Arithmetic Logic Unit that takes two input of 8 Bits each and undergoes 8 different operations and generates an output of 16 Bits
User: maazm007
vlsi-design,VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
User: maazm007
vlsi-design,BRACU CSE460 Lab (Summer 2020)
User: mehadihn
vlsi-design,A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
User: meiniki
vlsi-design,This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
User: mihir8181
vlsi-design,This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals required for the operation of washing machine and is designed using Verilog HDL.
User: mnmhdanas
vlsi-design,UART - RTL Design and Verification
User: mnmhdanas
vlsi-design,Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is referred to as universal shift register.
User: mnmhdanas
vlsi-design,Interfacing of FPGA & HPS on DE1-SoC.
User: nainshree-raj
vlsi-design,This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
User: neeraj1397
vlsi-design, I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.
User: orsuvenkatakrishnaiah1235
vlsi-design,NGspice netlist files for simulation of analog and digital circuits.
User: pankajpatro703
vlsi-design,Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
Organization: paripath
vlsi-design,THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE
User: parmashu
vlsi-design,Contains vim dotfiles configured for verilog, C++ & some stuff for VLSI
User: rithiknambiar
vlsi-design,VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
User: rohankalbag
vlsi-design,This repo contains golden vector and randomization testbenches for SRAM module.
User: saadia-hassan
vlsi-design,This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela
User: sagniknitr
vlsi-design,Repository containing the simulated schematics of logic gates, counters, adders and registers along with corresponding layouts for semiconductor design.
User: sathyasris27
vlsi-design,BRACU CSE460: VLSI Design Lab, Fall- 2021
User: shahriarkhanlimon
vlsi-design,Domain Specific Hardware Accelerators - VLSI CAD Project
User: sooryakiran
vlsi-design,Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
User: srohit0
Home Page: http://amzn.to/2paZ53b
vlsi-design,In electronics, a flip-flop is a special type of gated latch circuit. There are several different types of flip-flops. The most common types of flip flops are:TFF,DFF,JKFF,SRFF
User: suhailahamed2000
vlsi-design,Gatery, a library for circuit design.
Organization: synogate
Home Page: https://www.synogate.com/gatery.html
vlsi-design,Template project for using gatery
Organization: synogate
Home Page: https://www.synogate.com/gatery.html
vlsi-design,Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
User: tharunchitipolu
vlsi-design,Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
User: twweeb
vlsi-design,Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.
User: valendrew
vlsi-design,RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
User: vishakha7501
vlsi-design,Microshift Compression: An Efficient Image Compression Algorithm for Hardware
User: zhangmozhe
vlsi-design,Spiking Neural Network Accelerator
User: zwhexplorer
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