Comments (2)
cliffordwolf
commented on July 18, 2024
Thanks for bringing this to my attention! Usually I run "make test" before pushing to github but today morning I was in a hurry and skipped it..
I've now reported the bug in ABC and committed a workaround in Yosys. I will close this issue when the underlying bug in ABC is fixed.
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cliffordwolf
commented on July 18, 2024
The problem here was that ABC does not like networks with no primary inputs. But unused primary inputs are no problem, so now the yosys 'abc' command passes an additional dummy input to ABC if needed, which fixed the problem.
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Related Issues (20)
- Parameters in other packages HOT 2
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
- Latch inferred for x signal HOT 4
- Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855
- Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors HOT 3
- Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports HOT 1
- Another out-of-memory problem with for loop
- synth_* passes should call `check -mapped`
- "ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design HOT 2
- Crash in yosys-abc
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