Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports about yosys HOT 1 CLOSED

/* Generated by Yosys 0.40+7 (git sha1 7bb274620, c++ 15.0.0 -fPIC -Os) */

module top(wire1, wire2, wire3, y);
  wire _0_;
  wire _1_;
  wire _2_;
  wire _3_;
  inout wire1;
  wire wire1;
  input wire2;
  wire wire2;
  input wire3;
  wire wire3;
  output y;
  wire y;
  INV _4_ (
    .I(_3_),
    .O(_0_)
  );
  IOBUF _5_ (
    .I(_2_),
    .IO(wire1),
    .O(_1_),
    .T(_0_)
  );
  IBUF _6_ (
    .I(wire2),
    .O(_2_)
  );
  IBUF _7_ (
    .I(wire3),
    .O(_3_)
  );
  OBUF _8_ (
    .I(_1_),
    .O(y)
  );
endmodule