Comments (3)
cliffordwolf
commented on July 18, 2024
Unfortunately I don't have an OpenBSD installation to test, but I think I might have fixed the problem in commit 75a5d6b. Please give it a try and let me know if this fixed the problem.
from yosys.
bentley
commented on July 18, 2024
Nope, that gives the exact same error.
from yosys.
cliffordwolf
commented on July 18, 2024
I've now installed OpenBSD in a virtual machine and it seems like the fix worked just fine, but there is a similar problem about 100 lines later with stdout. I've now fixed that in a5a519a.
There are of course still problems with other source files, but register.cc now compiles fine on OpenBSD 5.5. I'm looking forward to pull requests and/or issues regarding the other build problems on OpenBSD.
from yosys.
Related Issues (20)
- Parameters in other packages HOT 2
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
- Latch inferred for x signal HOT 4
- Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855
- Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors HOT 3
- Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports HOT 1
- Another out-of-memory problem with for loop
- synth_* passes should call `check -mapped`
- "ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design HOT 2
- Crash in yosys-abc
- Manual title page should have yosys version number
- Should -nomx8 be the default for the GateMate?
- opt: no "-purge" option but public names removed HOT 2
- Tests fails on Debian GNU/Linux on ppc64 HOT 6
- write_smt2: "-wires" option leads to inequivalent descriptions
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
- Inout can't be read with constant value HOT 3
- Inout port not working with array replication operator HOT 6
- Add support for SystemVerilog's `==?` and `!=?` operators
Recommend Projects
-
React
A declarative, efficient, and flexible JavaScript library for building user interfaces.
-
Vue.js
🖖 Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
-
Typescript
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
-
TensorFlow
An Open Source Machine Learning Framework for Everyone
-
Django
The Web framework for perfectionists with deadlines.
-
Laravel
A PHP framework for web artisans
-
D3
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
-
Recommend Topics
-
javascript
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
-
web
Some thing interesting about web. New door for the world.
-
server
A server is a program made to process requests and deliver data to clients.
-
Machine learning
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
-
Visualization
Some thing interesting about visualization, use data art
-
Game
Some thing interesting about game, make everyone happy.
Recommend Org
-
Facebook
We are working to build community through open source technology. NB: members must have two-factor auth.
-
Microsoft
Open source projects and samples from Microsoft.
-
Google
Google ❤️ Open Source for everyone.
-
Alibaba
Alibaba Open Source for everyone
-
D3
Data-Driven Documents codes.
-
Tencent
China tencent open source team.
from yosys.