Comments (5)
You must post the complete reproduction steps, not just your Verilog code.
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Hi @whitequark, thank you for your quick response! I adapted the post according to your feedback. Please let me know if you would like more information!
from yosys.
I think 0x90beaf8
is expected, at least that's what I get with
yosys -p "read_verilog -sv top.sv; eval -set in_data 64'h216231b1f16e9e8 w:out_data"
Though there's still a discrepancy, since CXXRTL gives me 0x435522118
.
from yosys.
@flaviens I cannot reproduce this, and the condition ("intersection between operands") doesn't even make sense. 0x90beaf8
is the correct result.
>>> hex((0x216231b1f16e9e8>>6) & ((1 << (41-6+1))-1))
'0xc6c7c5ba7'
>>> hex((0x216231b1f16e9e8>>28) & ((1 << (63-28+1))-1))
'0x216231b1'
>>> hex(0xc6c7c5ba7 % 0x216231b1)
'0x90beaf8'
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This was probably fixed by commit ded63be and/or ff53f3d and/or d7cb698.
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Related Issues (20)
- Parameters in other packages HOT 2
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
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- Inconsistency in Verilog Synthesis: Yosys Successfully Synthesizes Code That Fails in Vivado and Quartus Due to Syntax Errors HOT 3
- Yosys Fails to Synthesize Tri-State Logic Correctly for inout Ports HOT 1
- Another out-of-memory problem with for loop
- synth_* passes should call `check -mapped`
- "ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2143" when using synth_{ice40,ecp5} on simple design HOT 2
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- write_smt2: "-wires" option leads to inequivalent descriptions
- Spurious warnings "select out of bounds on signal" when there is no such thing ... HOT 1
- Inconsistent simulation before and after yosys synthesis HOT 1
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- Inout port not working with array replication operator HOT 6
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