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Comments (5)

whitequark avatar whitequark commented on July 18, 2024

You must post the complete reproduction steps, not just your Verilog code.

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flaviens avatar flaviens commented on July 18, 2024

Hi @whitequark, thank you for your quick response! I adapted the post according to your feedback. Please let me know if you would like more information!

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povik avatar povik commented on July 18, 2024

I think 0x90beaf8 is expected, at least that's what I get with

yosys -p "read_verilog -sv top.sv; eval -set in_data 64'h216231b1f16e9e8 w:out_data"

Though there's still a discrepancy, since CXXRTL gives me 0x435522118.

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whitequark avatar whitequark commented on July 18, 2024

@flaviens I cannot reproduce this, and the condition ("intersection between operands") doesn't even make sense. 0x90beaf8 is the correct result.

>>> hex((0x216231b1f16e9e8>>6) & ((1 << (41-6+1))-1))
'0xc6c7c5ba7'
>>> hex((0x216231b1f16e9e8>>28) & ((1 << (63-28+1))-1))
'0x216231b1'
>>> hex(0xc6c7c5ba7 % 0x216231b1)
'0x90beaf8'

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whitequark avatar whitequark commented on July 18, 2024

This was probably fixed by commit ded63be and/or ff53f3d and/or d7cb698.

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