zishuoyang / ut-backplane-mapping Goto Github PK

@ZishuoYang we talked about this with Tom yesterday, but I forgot the details, could you define what we need to do here?

Also about how to treat differential pairs and other stuffs.

TrueType:

When inspecting the backplaneMapping_SEAMPins_trueType_v4.1.xlsm, I noticed that there are 2 headers with the same name SEAM pin (one in cell C5, the other K5).

Please specify the meaning of each header.

• Update input/mapping_strategy.yml
• See if it possible to further compactify the data GBTx assignments
• Provide all rules needed for a remap

So far we prefer pCad netlist, since it looks like a lisp program, which is very easy to parse. Tom was suggesting some alternative format, the name which I forget.

Currently the netlist check reports the following:

The following net is missing in the implementation: JP0_JT1_P3_LV_SENSE_P
The following net is missing in the implementation: JP0_JT1_P4_LV_SENSE_P
The following net is missing in the implementation: JP0_JT1_P4_LV_SENSE_N
The following net is missing in the implementation: JP0_JT1_P3_LV_SENSE_N
The following net is missing in the implementation: JP2_JT0_P3_LV_SENSE_P
The following net is missing in the implementation: JP2_JT0_P4_LV_SENSE_P
The following net is missing in the implementation: JP2_JT0_P4_LV_SENSE_N
The following net is missing in the implementation: JP2_JT0_P3_LV_SENSE_N>

This should not happen because we expect JT0 to associate with JP0-3, etc..

Update: this has been fixed in our script -- no longer reporting similar inconsistency.

Some additional inconsistencies:

• CP: JP0_FRO_P3_LV_SENSE_GND, implemented: JP4F05_P2_EAST_LV_SENSE_GND, and other 54 LV_SENSE_GND entries.
• CP: JP8_JPU2_P4_LV_RETURN, implemented: JP8_JPL2_P4_LV_RETURN (only 1).
• CP: *OUT*, JDX_B1, JDX_B3, implemented: None

So far, in the implementation, we have a net called JD9_JPL2_1V5 that contains JD8 nodes, but it is not flagged by our checker.

With DCB secondary controls eliminated, Mirror-Type schematic may be generated by simply swapping all assignments' connector indices on True-Type schematic. A table can clearly show the swap.

We can add an additional automated check to the existing code, for depopulation resistors' reference designator flags, as described in the #18 (comment).

What Phoebe suggested on Slack, "no Rx should be attached to a line that ends up on a pigtail connector (ie is used in some variant) except for ground sense", is to get all the nets with a PT pin and check that there's no resistor present except for on ground sense lines. But this has to be done while identifying what nets should be active on a given variant. Because we are checking the netlist, we risk going in to a circle here to use the depopulation resistors for identifying active nets in the first place.

I think the more practical way is to:

• make sure that the existing code to generate the depopulation auxiliary list is correct
• then inspect the netlist and compare the names of nets with depopulation resistors against the auxiliary list

In the mean time, I have checked both True and Mirror schematics by eye. See details in the lab-notes issue post.

I finally got a working script that can partially reconstruct your original test_AltiumNetlist_PT.CSV. However, I found the following issues regarding these LV_*.

For example, for Pigtail slot 0, pin A06, my result would be:
JP0_JPU0_P2_EAST_LV_RETURN,0,A06,,
whereas yours is:
JP0_JPU0_P2_EAST_LV_RETURN,,,,

Upon inspecting your script, I found the following snippet:

elif ('LV_SOURCE' in net[6]):
    replaced = False
    for a in range(0,len(list_BOB)):
        if list_BOB[a]=='GND' or list_BOB[a]=='': continue
        if ( ('JP'+net[3]) in list_BOB[a].split('_') ) and ( net[6] in list_BOB[a] ) :
            print(list_BOB[a] + ',' +net[3]+','+net[4]+net[5]+','+''+','+'')
            replaced=True
    if replaced==False:
        print('JP'+net[3]+net[4]+net[5]+'_ForRefOnly_'+net[6]+ ',' +net[3]+','+net[4]+net[5]+','+''+','+'')

which led me to believe that mine is the correct behavior.

v5.2 has been issued for trueType mapping. The same needs to be done on the mirrorType, to correct the error made on DCB boards.

In backplane_mapping_PT.yml, the PT pins noted 'Alpha only' are not consistent with the blue-highlighted
pins in PT Excel. This results in the auxiliary list including many entries that should not be depopulated.

e.g. JP0,A12 is noted 'Alpha only', but in Excel it is solid-black not blue.

In the latest commit:

...for pt_id in range(0, len(pt_descr)):
    for pt_entry in pt_descr[pt_id]:
        if pt_entry['Signal ID'] is not None \
                and (pt_entry['Signal ID'].endswith('SCL_N') or
                     pt_entry['Signal ID'].endswith('SDA_N') or
                     pt_entry['Signal ID'].endswith('RESET_N')):

There is no parenthesis after the second and. These ors might not be behave as intended.

We see outdated DCB indices on Mirror BPs, while True BPs seem consistent. For example, on Magnet-Bottom-C, the DCB indices corresponding to pigtail X-0-M are shown to be 0/1/3, while we know the swapped indices on the BP schematics are 0/1/2.

within a DCB column, some GBTx can be swapped to increase common number of signals between the 4x4 groupings

• SDA and SCL are flipped. (need to change in both pigtail and dcb mapping Excel docs).
  Edit: I have updated the trueType mapping Excel to v5.2, and pushed the changes. - ZSY

• input/BrkOutBrd_Pin_Assignments_..._.xls needs to be completely updated, because Tom has changed almost everything related on the schematic. Tom did not update the Excel file, so we need to copy and paste from Altium. Not surprisingly, Altium's copy as text function does not preserve the order, so anticipate some hours wasted here. To check if telemetry JT pins changed.
  Edit: This has been updated by me and double-checked by Tom. (Did not find JT change, although Tom mentioned he'd add GND there are. But GND on JT should be transparent to mapping.) - ZSY

• THERMISTOR_N in Tom's list is connected to AGND (need to change our source code/change manually).
  This single DCB pin is connected to multiple PigTail pins (because AGND is on DCB).
  Edit: Tom agreed to leave this case for manual editing.

• A few cases of shortening THERMISTOR to THERM.

• naming inconsistency, Zishuo: JP0_UNUSED; Tom: GND; e.g. JP pins B29, C29, D29, E29, E34, I10
  This means adding a rule that assign GND instead of UNUSED.

• naming inconsistency: for single-ended signals HYB_i2C/EC_RESET/EC_ADC, Tom appended _P to the signal ID.
  Edit: This is addressed by adding a new rule, RulePT_PTSingleToDiff. For EC_ADC, Tom also added prefix THERM to signal ID

• Some naming inconsistencies for unconnected pins, expected since to be tied to GND.
  Using vim command :%s/Tom\: GND\; node\: DCB\: None//n, 514 out of 1085 warnings seem to be of this type.
  This is addressed by classifying Signal ID, and change their rules to give GND:

• • _ASIC_: if unconnected, always ground
• • _CLK_: if unconnected, always ground
• • _TFC_: if unconnected, always ground
• • _THERMISTOR_: if unconnected, always ground
• • _I2C_ & _RESET_: if _P unconnected, always ground; if _P connected, _N need to connect to ??

• For pins that are grayed-out in Excel (not used), they should always be GND. So we generalize the Unused rule to select Signal IDs with excel font_color.tint != 0.0, and make them GND.

• Tom has some JD_JP with no DCB pin, e.g.netlist name inconsistent: Zishuo: JP0_P1_EAST_I2C_SDA_N; Tom: JD2_JP0_EC_HYB_i2C_SDA_5_N; node: DCB: None, DCB_PIN: None, PT: JP0, PT_PIN: H9

• netlist name inconsistent: Zishuo: JP0_P1_WEST_RESET_N; Tom: JD0_JP0_EC_RESET_GPIO_5_N; node: DCB: None, DCB_PIN: None, PT: JP0, PT_PIN: I22

• node in NET JD4_JP0_EC_ADC_5 not present in Tom's net: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24. This is probably due to component entering between the nodes. Edit: This is also caused by telemetry connection as below.

• THERMISTOR_P assigned as e.g. JP0_JT0_P1_EAST_THERM_P by Tom, but as JD2H46_JP0J12_EC_ADC_7 by Zishuo
  This is due to the change of rule for some P_THERMISTOR: for 8-ASIC hybrids, the EAST of two thermistors is rerouted to JT telemetry board, e.g. JP1_JT0_P1_EAST_THERM_P, JP1_JT0_P1_EAST_THERM_P, JP0_JT0_P1_EAST_THERM_P. Specifically, for the original JD2H46-JP0J12 connection, because JP0J12=JP0_P1_EAST_THERM_P, now it's JP0J12-JT0XX and JD2H46_FRO.
  Proposed solution: change of rule to overwrite original connection, by matching JP + SigID on table JT in BrkOutBrd_Pin_Assignments.xlsx, and give ForReferenceOnly attribute to JD_EC_ADC pin.
  Edit: Tom agree to do this by hand.

error log after excluding understood types:

====ERRORS for Backplane connections====
========Not Implemented by Tom========
NOT present in Tom's net: NET: JD4_JP0_P2_EAST_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: A5
NOT present in Tom's net: NET: JD4_JP0_P4_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: B24
NOT present in Tom's net: NET: JD4_JP0_THERM_EC_ADC_5_P, NODE: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24
NOT present in Tom's net: NET: JD4_JP0_P3_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP0, PT_PIN: E14
NOT present in Tom's net: NET: JD2_JP0_P1_EAST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP0, PT_PIN: I12
NOT present in Tom's net: NET: JD0_JP0_P1_WEST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP0, PT_PIN: I27
NOT present in Tom's net: NET: JD2_JP0_THERM_EC_ADC_7_P, NODE: DCB: JD2, DCB_PIN: H46, PT: JP0, PT_PIN: J12
NOT present in Tom's net: NET: JD0_JP1_P2_EAST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP1, PT_PIN: A5
NOT present in Tom's net: NET: JD0_JP1_THERM_EC_ADC_3_P, NODE: DCB: JD0, DCB_PIN: H38, PT: JP1, PT_PIN: B5
NOT present in Tom's net: NET: JD4_JP1_P4_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP1, PT_PIN: B24
NOT present in Tom's net: NET: JD2_JP1_P2_WEST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP1, PT_PIN: B40
NOT present in Tom's net: NET: JD4_JP1_P3_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP1, PT_PIN: E14
NOT present in Tom's net: NET: JD2_JP1_P1_EAST_THERMISTOR_N, NODE: DCB: JD2, DCB_PIN: H40, PT: JP1, PT_PIN: I12
NOT present in Tom's net: NET: JD0_JP1_P1_WEST_THERMISTOR_N, NODE: DCB: JD0, DCB_PIN: H40, PT: JP1, PT_PIN: I27
NOT present in Tom's net: NET: JD2_JP1_THERM_EC_ADC_5_P, NODE: DCB: JD2, DCB_PIN: H42, PT: JP1, PT_PIN: J12
NOT present in Tom's net: NET: JD1_JP2_P2_EAST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP2, PT_PIN: A5
NOT present in Tom's net: NET: JD5_JP2_P4_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP2, PT_PIN: B24
NOT present in Tom's net: NET: JD3_JP2_P2_WEST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP2, PT_PIN: B40
NOT present in Tom's net: NET: JD5_JP2_P3_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP2, PT_PIN: E14
NOT present in Tom's net: NET: JD3_JP2_P1_EAST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP2, PT_PIN: I12
NOT present in Tom's net: NET: JD1_JP2_P1_WEST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP2, PT_PIN: I27
NOT present in Tom's net: NET: JD5_JP3_P2_EAST_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: A5
NOT present in Tom's net: NET: JD5_JP3_P4_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: B24
NOT present in Tom's net: NET: JD5_JP3_P3_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP3, PT_PIN: E14
NOT present in Tom's net: NET: JD3_JP3_P1_EAST_THERMISTOR_N, NODE: DCB: JD3, DCB_PIN: H40, PT: JP3, PT_PIN: I12
NOT present in Tom's net: NET: JD1_JP3_P1_WEST_THERMISTOR_N, NODE: DCB: JD1, DCB_PIN: H40, PT: JP3, PT_PIN: I27
NOT present in Tom's net: NET: JD6_JP4_P2_EAST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: A5
NOT present in Tom's net: NET: JD8_JP4_P4_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP4, PT_PIN: B24
NOT present in Tom's net: NET: JD8_JP4_P3_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP4, PT_PIN: E14
NOT present in Tom's net: NET: JD6_JP4_P1_EAST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: I12
NOT present in Tom's net: NET: JD6_JP4_P1_WEST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP4, PT_PIN: I27
NOT present in Tom's net: NET: JD8_JP5_P2_EAST_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP5, PT_PIN: A5
NOT present in Tom's net: NET: JD8_JP5_P3_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP5, PT_PIN: E14
NOT present in Tom's net: NET: JD4_JP5_P1_EAST_THERMISTOR_N, NODE: DCB: JD4, DCB_PIN: H40, PT: JP5, PT_PIN: I12
NOT present in Tom's net: NET: JD6_JP5_P1_WEST_THERMISTOR_N, NODE: DCB: JD6, DCB_PIN: H40, PT: JP5, PT_PIN: I27
NOT present in Tom's net: NET: JD9_JP6_P2_EAST_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP6, PT_PIN: A5
NOT present in Tom's net: NET: JD9_JP6_P3_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP6, PT_PIN: E14
NOT present in Tom's net: NET: JD5_JP6_P1_EAST_THERMISTOR_N, NODE: DCB: JD5, DCB_PIN: H40, PT: JP6, PT_PIN: I12
NOT present in Tom's net: NET: JD7_JP6_P1_WEST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP6, PT_PIN: I27
NOT present in Tom's net: NET: JD7_JP7_P2_EAST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: A5
NOT present in Tom's net: NET: JD9_JP7_P4_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP7, PT_PIN: B24
NOT present in Tom's net: NET: JD9_JP7_P3_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP7, PT_PIN: E14
NOT present in Tom's net: NET: JD7_JP7_P1_EAST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: I12
NOT present in Tom's net: NET: JD7_JP7_P1_WEST_THERMISTOR_N, NODE: DCB: JD7, DCB_PIN: H40, PT: JP7, PT_PIN: I27
NOT present in Tom's net: NET: JD10_JP8_P2_EAST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: A5
NOT present in Tom's net: NET: JD10_JP8_P4_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: B24
NOT present in Tom's net: NET: JD10_JP8_P3_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP8, PT_PIN: E14
NOT present in Tom's net: NET: JD8_JP8_P1_WEST_THERMISTOR_N, NODE: DCB: JD8, DCB_PIN: H40, PT: JP8, PT_PIN: I27
NOT present in Tom's net: NET: JD10_JP9_P2_EAST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: A5
NOT present in Tom's net: NET: JD10_JP9_P3_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: E14
NOT present in Tom's net: NET: JD10_JP9_P1_WEST_THERMISTOR_N, NODE: DCB: JD10, DCB_PIN: H40, PT: JP9, PT_PIN: I27
NOT present in Tom's net: NET: JD11_JP10_P2_EAST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: A5
NOT present in Tom's net: NET: JD11_JP10_P3_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: E14
NOT present in Tom's net: NET: JD11_JP10_P1_WEST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP10, PT_PIN: I27
NOT present in Tom's net: NET: JD11_JP11_P2_EAST_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: A5
NOT present in Tom's net: NET: JD11_JP11_P4_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: B24
NOT present in Tom's net: NET: JD11_JP11_P3_THERMISTOR_N, NODE: DCB: JD11, DCB_PIN: H40, PT: JP11, PT_PIN: E14
NOT present in Tom's net: NET: JD9_JP11_P1_WEST_THERMISTOR_N, NODE: DCB: JD9, DCB_PIN: H40, PT: JP11, PT_PIN: I27

========DCB-None or None-PT========

========For Reference Only========

Not implemented telemetry:

NOT present in Tom's net: NET: JD4_JP0_THERM_EC_ADC_5_P, NODE: DCB: JD4, DCB_PIN: H42, PT: JP0, PT_PIN: C24
NOT present in Tom's net: NET: JD2_JP0_THERM_EC_ADC_7_P, NODE: DCB: JD2, DCB_PIN: H46, PT: JP0, PT_PIN: J12
NOT present in Tom's net: NET: JD0_JP1_THERM_EC_ADC_3_P, NODE: DCB: JD0, DCB_PIN: H38, PT: JP1, PT_PIN: B5
NOT present in Tom's net: NET: JD2_JP1_THERM_EC_ADC_5_P, NODE: DCB: JD2, DCB_PIN: H42, PT: JP1, PT_PIN: J12

We received a report on mismatched differential signal:
JD10_JP9_P2_EAST_THERMISTOR_N, JD10_JP9_THERM_EC_ADC_3_P.

According to @ZishuoYang , currently these signals can be classified into 2 types, and the classification is to be manually determined. So we need some input on the classification of these signals.

After the True-type schematic has been implemented, it might be possible for us to learn from the classification, and implement such classification into the Mirror-type copy-paste rule.

I claim that if we reuse the pt_result_true and dcb_result_true to generate Excel, it would be relatively easy.

The problem is that the signal IDs on the PT side have been replaced by DCB side. I'm wondering if it is OK to do so?

Some of the connection properties are defined by color, and Excel chose to implement visually identical colors with different mark up. It is increasingly hard to parse Excel, and we decide to convert Excel to yaml.

• Convert Tom's additional signals Excel to yaml.
• Write helpers to make manipulating dict-list-dict easier.
• Convert Jason/Zishuo's PT and DCB Excel to 2 yaml files.

Perhaps more importantly, we need to make sure Excel and yaml readers produce similar results, so that this conversion is transparent to established code:

• Make sure the yaml reader produces results similar to that of Excel reader.

Currently:

    if True in map(lambda x: bool(re.search(r'^JP8|^JP9|^JP10|^JP11', x[0])), components):
        if True not in map(lambda x: bool(re.search(r'^RB_\d+|^RBSP\d+|^RxCB_\d+', x[0])), components):
            print("No depopulation component found in {}".format(diff_net))
    # for Beta variant:
    else:
        if True not in map(lambda x: bool(re.search(r'^RB_\d+|^RBSP\d+|^RxCB_\d+', x[0])), components):
            print("No depopulation component found in {}".format(diff_net))

The re.search part is the same for both beta and beta special.

According to backplaneMapping_SEAMPins_trueType_v5.2.xlsm, BLUE trace depopulates on middle and outer backplane.

First, I would assume BLUE means blue in Pigtail slot and GBTx ID. However, for JD4, there are some blue entries for GBTx ID, but their corresponding Pigtail slot are not in blue.

For True-Type:

• X: hybrid is present on both Alpha and Beta (but may depopulate a few ELKs)
• O: hybrid is depopulated on Beta
• blank: not present

Nets_Being_Questioned_FullTrueBP_Jan18_2019.pdf

As titled, to extend the current fiber mapping header and include:

• DCB channel for DC_OUT_RCLK#_P (for JP signal e.g. P#_EAST_CLK_P)
• DCB channel for EC_HYB_i2C_SCL_# (for JP signal e.g. P#_EAST_I2C_SCL_P)
• DCB channel for EC_HYB_i2C_SDA_# (for JP signal e.g. P#_EAST_I2C_SDA_P)
• DCB channel for EC_RESET_GPIO_# (for JP signal e.g. P#_EAST_RESET_P)
• DCB channel for MC_TFC#_P (for JP signal e.g. P#_EAST_TFC_P)
• DCB channel for EC_ADC_# (for JP signal e.g. P#_EAST_THERMISTOR_P)

Note that each set of these channels is for one 4-ASIC group (e.g. P1_EAST).

Two categories of possible errors have been checked at the time the mapping Excel docs were finalized:

• Errors due to pin-assigning in the process of mapping each net/connection:

1. Check that polarity is correct: _N/P of one pin matches _N/P of the other pin.
2. Check if the mapped pins have the same type of signal ID: e.g. Pigtail's signal ID (ASIC_CH) agrees with DCB’s signal ID (DC_ELK).
3. Check that connector pins in the two list match.
4. Check if a specific pin on a specific connector is used more than once.

• Errors due to violating design rules, for each type of signals:

1. Check the Elink Packing Order between EC_ELK and ASIC_CH
   • For each ASIC, find the 1st ELK and check that with increasing ASIC channel number, ELK channel number decreases.
2. Check MC_SEC connects to EC_SEC (No longer used)
3. Check MC_TFC connects to Hybrids on the assigned connectors the number of signals
4. Check DC_OUT_RCLK (from DCs to Hybrids) on the assigned connectors and the number of signals
5. Check EC_RESET connects to DC and Hybrids on the assigned connectors and the number of signals
6. Check EC_HYB_i2C (from SCA to Hybrids) on the assigned connectors and the number of signals
7. Check EC_ADC connects to Hybrid thermistors on the assigned connectors and the number of signals