Hi,
I had originally posted the issue under TritonSizer (here), but i just realized its likely an OpenSTA issue.

On CentOS7, upon make, it gives:

Making directory /home/user/Downloads/openflow/TritonSizer/module/tcl/unix/install-sp/man/man3
Making directory /home/user/Downloads/openflow/TritonSizer/module/tcl/unix/install-sp/man/mann
Installing and cross-linking top-level (.1) docs
Installing and cross-linking C API (.3) docs
Installing and cross-linking command (.n) docs
make[1]: Leaving directory '/home/user/Downloads/openflow/TritonSizer/module/tcl/unix'
cd module/OpenSTA && mkdir -p install-sp &&
./bootstrap && ./configure --prefix=/home/user/Downloads/openflow/TritonSizer/module/OpenSTA/install-sp
--with-lib=/home/user/Downloads/openflow/TritonSizer/module/tcl/unix/install-sp/lib
--with-include=/home/user/Downloads/openflow/TritonSizer/module/tcl/unix/install-sp/include
--with-tcl=/home/user/Downloads/openflow/TritonSizer/module/tcl/unix/install-sp/lib/tcl8.4 &&
make install;
/bin/sh: line 1: ./bootstrap: No such file or directory
make: *** [Makefile:14: sta] Error 127

There s no bootsrap file in OpenSTA directory

Hi,
I am trying to synthesize a data and clock recovery module, and i am getting trouble constraining the design. Simplified testcase (ran with sta in standalone, rev 09524cb) :
20200918.zip

I am defining the constraints like this:

create_clock -name clk -period 10 {clk}

create_generated_clock -name clk_gen -source clk -divide_by 2 r2/Q

set_propagated_clock [all_clocks]

set_input_delay -clock clk -min 0.1 {in1 in2}
set_input_delay -clock clk -max 6 {in1 in2}

#constraint clk_out wrt to clk
set_output_delay -clock clk -max 8  [get_ports clk_out]
set_output_delay -clock clk -min 0  [get_ports clk_out]
set_load -pin_load -min 0.005 [get_ports clk_out]
set_load -pin_load -max 0.1   [get_ports clk_out]

#constraint data_out wrt to clk_out
set_output_delay -reference_pin [get_ports clk_out]  -max 7    [get_ports data_out]
set_output_delay -reference_pin [get_ports clk_out]  -min 0.05 [get_ports data_out]
set_load -pin_load -min 0.005 [get_ports data_out]
set_load -pin_load -max 0.1   [get_ports data_out]

I am getting a warning saying data_out is unconstrained

check_setup -unconstrained
Warning: There is 1 unconstrained endpoint.
  data_out

But the timing path looks to be correctly calculated in relation with clk_out:

Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: data_out (output port clocked by clk_gen)
Path Group: clk_gen
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
----------------------------------------------------------------------------
                        10.00   10.00   clock clk (rise edge)
                         0.00   10.00   clock source latency
                 0.00    0.00   10.00 ^ clk (in)
    2    2.65                           clk (net)
                 0.00    0.00   10.00 ^ r1/CK (DFFR_X1)
                 0.01    0.10   10.10 ^ r1/Q (DFFR_X1)
    1    1.28                           r1q (net)
                 0.01    0.00   10.10 ^ u1/A (BUF_X1)
                 0.00    0.02   10.12 ^ u1/Z (BUF_X1)
    1    0.10                           data_out (net)
                 0.00    0.00   10.12 ^ data_out (out)
                                10.12   data arrival time

                        20.00   20.00   clock clk_gen (rise edge)
                         0.00   20.00   clock source latency
                 0.00    0.00   20.00 ^ clk (in)
    2    2.65                           clk (net)
                 0.00    0.00   20.00 ^ r2/CK (DFFR_X1)
                 0.01    0.10   20.10 ^ r2/Q (DFFR_X1)
    1    1.09                           clk_gen (net)
                 0.01    0.00   20.10 ^ u2/A (CLKBUF_X1)
                 0.01    0.02   20.12 ^ u2/Z (CLKBUF_X1)
    1    0.10                           clk_out (net)
                 0.01    0.00   20.12 ^ clk_out (out)
                         0.00   20.12   clock reconvergence pessimism
                        -7.00   13.12   output external delay
                                13.12   data required time
----------------------------------------------------------------------------
                                13.12   data required time
                               -10.12   data arrival time
----------------------------------------------------------------------------
                                 3.01   slack (MET)

Is there something wrong with my constraints or is it a bug for the unconstrained checks ?
Thanks

Relatively new to OpenSTA
I want to insert a buffer between net 03412 and load pin 33464/A2 as shown in below timing report snippet:

    Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.13    0.12    1.28 ^ _33458_/X (sky130_fd_sc_hd__buf_1)

 4             0.01                                     _03412_ (net)
                           0.13    0.00    1.28 ^ _33464_/A2 (sky130_fd_sc_hd__a21o_4)
                           0.01    0.08    1.36 ^ _33464_/X (sky130_fd_sc_hd__a21o_4)

Tried:

% help insert_buffer 
insert_buffer buffer_name buffer_cell net load_pins buffer_out_net_name
% 
% insert_buffer _my_buf_ sky130_fd_sc_hd__buf_4  _03412_  _33464_/A2  _my_net_
invalid command name "insert_buffer_cmd"

Can't really figure out where I'm going wrong. Also couldn't find any reference in the openSTA manual for this command. Any help is appreciated

Host for ftp://vlsi.colorado.edu/pub/ doesn't resolve.

Sorry to recreate the issue. When compiling with 983149a, everything works.
However, after bdd7468, the NaN's are back.
Going through the code, it would appear that issue is here:

I tested the fix nan2.txt on c43b426 and it correctly suppresses the NaN's.

Thanks for your help,
Peter

Hello,

trying to build a port which uses the OpenSTA API (TritonSizer), I noticed that the header file util/StaConfig.hh is missing in the list of files to be installed (this breaks the code in multiple places).

I solved with the following simple patch:

Index: CMakeLists.txt
--- CMakeLists.txt.orig
+++ CMakeLists.txt
@@ -366,6 +366,7 @@ set(STA_HEADERS
   util/ReportStd.hh
   util/ReportTcl.hh
   util/Set.hh
+  util/StaConfig.hh
   util/Stats.hh
   util/StringSeq.hh
   util/StringSet.hh

Several systems have ports for OpenSTA: https://repology.org/project/opensta/versions, but port maintainers have to make up version numbers because here on GitHub no version number is assigned.

Could you please make a release and assign a version number so that people can track changes in the project?

Thank you.
Yuri

Hi James
Currently, I am working on correlating top 10000 max and min paths from OT with openSTA for 180nm, so as to use openSTA for production chips. Do you have any predefined correlation scripts or predefined settings, which you might have used for something similar?

PS - I am submitting this as an 'issue' as I don't see an option of a 'question' in github

Hi James
Is there any single command (or group of commands) which will give below information? The numbers in the right are just an example from an internal design

Instance count | 229861
worst setup slack(ns) | -42.9503
worst hold slack(ns) | -0.7841
no. of paths analyzed (setup/hold) | 129315
total setup slack(ns) | -1212078.875
total hold slack(ns) | -1902.4175
Design Area(um2) | 9727901
total trans violations(ns) | -52366.2148
total max_cap violations(fF) | -1138.5537

Hi James
I am using below command to set_wire_load_model, but its setting only for top and not for hierarchical instances
current_design mkSoc_wrapper
set_wire_load_model -name ForQA -library tsl18fs120_scl_ss
Is there a way I can set_wire_load_model to top and all instances as well?

Hi James,

I'm trying to compile OpenSTA on MacOS with Mac Ports installation of libraries -- in particular CUDD. I found my MacPort installation of cudd located at /opt/local/include/cudd (for headers) and /opt/local/lib/cudd (for the library).

I had to modify CMakeLists.txt to be:
Because I am using MacPorts, the CUDD package is installed in /opt/local, with include files in /opt/local/include/cudd and library at /opt/local/lib/cudd/libcudd*.

To allow me to set CUDD_INCLUDE, I needed to modify CMakeLists.txt to read:

if("${CUDD}" STREQUAL "" OR "${CUDD}" STREQUAL "0")
set(CUDD_INCLUDE "")
set(CUDD_LIB "")
set(CUDD_FOUND FALSE)
set(CUDD 0)
message(STATUS "CUDD library: not found")
else()
if("${CUDD_INCLUDE}" STREQUAL "") <<==changed lines
set(CUDD_INCLUDE ${CUDD}/include) <<==changed lines
endif() <<==changed lines
find_library(CUDD_LIB NAMES cudd PATHS ${CUDD}/lib)
if (CUDD_LIB)
# CUDD referenced by StaConfig.hh.cmake
set(CUDD 1)
message(STATUS "CUDD library: ${CUDD_LIB}")
message(STATUS "CUDD header: ${CUDD_INCLUDE}")
endif()
endif()

Then, with the command line for cmake:

cmake .. -DCUDD_LIB=/opt/local/lib/cudd/libcudd.dylib -DTCL_LIB=/opt/local/lib/libtcl.dylib -DZLIB_ROOT=/opt/local/lib/libz.dylib -DCUDD_INCLUDE=/opt/local/include/cudd

I was able to pass the "missing cudd header file" and build "sta".

George

The project installs 164 files into /usr/local/include. It's better if they would go into a dedicated subdirectory, for example /usr/local/include/opensta. Fewer files would be in include/, and the possibility of conflicts with other packages would also be lower.

Hi,
It would be nice to have support for command history using up/down keys.
I have a patch available, basically a copy of what's done in the OpenROAD repository (issue 136). Let me know if I should open a pull request.

I have just come across an issue with Yosys, where it produces assigns like the following:

assign {a,b} = {c,d};

OpenSTA cannot parse these.

Now, the simple approach would be to stop Yosys generating such assigns, since they could always be separated into multiple assign statements. I think the issue has been raised before with Clifford, and he points out that it is legal verilog. I will raise it with him again, though.

Fixing the OpenSTA parser would be great, but I suspect that might be a tricky job ..

Unfortunately, it is quite difficult to generate a simple example; whether or not such constructs are generated is highly dependent on the steps used in yosys.

Hello,

compiling OpenSTA on OpenBSD (usign either clang 7.0.1 or gcc 4.9.4) I see the following errors:

/usr/ports/pobj/opensta-20190325/OpenSTA-e141c83b2ea1cee8f9414a5733c924e9fb2943e4/app/StaApp_wrap.cc:1087:49: error: reinterpret_cast from 'nullptr_t' to 'char *' is not allowed
    if (Tcl_VarEval(interp,"info commands ", c, reinterpret_cast<char*>(NULL)) == TCL_OK) {
                                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/ports/pobj/opensta-20190325/OpenSTA-e141c83b2ea1cee8f9414a5733c924e9fb2943e4/app/StaApp_wrap.cc:1102:45: error: reinterpret_cast from 'nullptr_t' to 'char *' is not allowed
    if (Tcl_VarEval(interp,c," cget -this", reinterpret_cast<char*>(NULL)) != TCL_OK) {
                                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~

They can be easily solved by using static_cast instead of reinterpret_cast as per the following trivial patch:

Index: etc/SwigCleanup.tcl
--- etc/SwigCleanup.tcl.orig
+++ etc/SwigCleanup.tcl
@@ -93,7 +93,7 @@ proc swig5 { line_var } {
     {, reinterpret_cast<char*>(ptr)} line
   
   regsub ", *\\\(char *\\\*\\\) NULL" $line \
-    {, reinterpret_cast<char*>(NULL)} line
+    {, static_cast<char*>(NULL)} line
     
   regsub ", ?\\\(char ?\\\*\\\)(\[^,\\\)\]+)(\[,\\\)\])" $line \
     {, const_cast<char*>(\1)\2} line

but I don't know if that can have any side effects. Could you please double check?

Thanks and regards

--
Alessandro

Hi

Thanks for this great contribution to the open source world!

I noticed there is one problematic statement that prevents inclusion into Debian. Would it be possible to "clean up" this one?
See CMakeLists.txt:

# No part of this document may be copied, transmitted or
# disclosed in any form or fashion without the express
# written consent of Parallax Software, Inc.

Cheers

When reading a verilog file with busses, I get errors like this:
Error: synthesis/raven_spi.rtlbb.v, line 8 syntax error, unexpected ';', expecting '='.

The read_liberty command reads a cell library, but it does not recognize memories. These require support for the memory cell type. You can see an example from OpenRAM at:

https://github.com/VLSIDA/OpenRAM/blob/master/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib

Let me know if you have any questions or if you have suggestions for adjusting memory lib files for use in OpenSTA.

Hi James,
I got the warnings below after executing read_liberty command.

Warning: axis type normalized_voltage not supported.
Warning: missing variable_2 attribute.

This is the lookup table which caused the warnings

lu_table_template (waveform_template_name) {
 variable_1: input_net_transition;
 variable_2: normalized_voltage;
 index_1 ("float…, float");
 index_2 ("float…, float");
 }

This variable is supported by Liberty format but may be unused here.
Should I just ignore the warning messages like these? Thanks!

Hi,
While i am giving a .spef file to openSTA, it shows error saying pin name not found.?
"Warning: ./synthesis/FIFO.mod.spef, line 1499 net CLK_bFbuf5 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1545 net CLK_bFbuf4 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1591 net CLK_bFbuf3 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1641 net CLK_bFbuf2 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1689 net CLK_bFbuf1 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1737 net CLK_bFbuf0 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1802 pin 61_1 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1803 pin 61_2 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1804 pin 61_3 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1805 pin 61_4 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1806 pin 61_5 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1807 pin 61_6 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1808 pin 61_7 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1809 pin 61_8 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1810 pin 61_9 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1811 pin 61_10 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1812 pin 61_11 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1813 pin 61_12 not found.
Warning: ./synthesis/FIFO.mod.spef, line 1814 pin 61_13 not found."

Above is the some portion of error at last the variable flag shows "1", & upon report_checks on same path, the arrival time decreases, which is expected to be increased.

Please let me know if i am processing something wrong in the procedure, else help me out of it.

I've been running into an issue with the report_power command. Some instances appear to have NaN for the internal power (Combinational). It appears to be traceable to the Power.cc file, on line 852 there is a comparison with 0.0 (which is what the activity in the to_pin is), but that comparison appears to result in 0.0 != 0.0. This is not 100% unexpected since it's a float comparison.

There is a second place in the Power.cc file that also makes a comparison with 0.0 on line 817.

I'm not sure if this was your intended use of fuzzyZero, but I saw it was there, so it was easy to use.

Please let me know if you need more information.

Thanks,
Peter

Whenever I'm sourcing the examples files, or reading them, with the command
OpenSTA> source example1.tcl

I'm getting error : cannot read this file
Same while reading

Dear developer,

I am trying to report multiple timing paths in different restrictions
report_checks -through PIN1 -through PIN2 -through PIN3
report_checks -through PIN4 -through PIN5 -through PIN6
...

I am stacking multiple report_checks in my command file, but I've got "Search.cc:2669 max tag group index exceeded" and "Segmentation fault" when the number of report_checks is over 7000. I would like to know the proper way to write my command file without getting this error.

Thanks

Dear developer,

I am using the report_checks command with -through and -to options to show top k critical paths involving through pins and destination pin. I can get k paths by using -endpoints k, but slacks of these paths are always INF if I choose to use the register input (commonly considered as a type of endpoint) as -to pin. I experimented this on a classic s27 design. The command I used is

report_checks -unconstrained -format end -endpoint_count 4 -through inst_6/A1 -to inst_16/D

I obtained the following result.

inst_16/D (DFFR_X2) INF 202.22 INF (MET)
inst_16/D (DFFR_X2) INF 181.02 INF (MET)
inst_16/D (DFFR_X2) INF 177.97 INF (MET)
inst_16/D (DFFR_X2) INF 153.33 INF (MET)

If I choose to use primary output pin G17 as -to pin. The slack values are valid.

G17 (output) -0.20 177.68 -177.88 (VIOLATED)
G17 (output) -0.20 174.15 -174.35 (VIOLATED)
G17 (output) -0.20 153.04 -153.24 (VIOLATED)
G17 (output) -0.20 138.33 -138.53 (VIOLATED)

I am not sure if I missed any steps or I used the wrong pin as -to pin. I have attached the entire design below. "s27.tcl" is the file I used as command file to OpenSTA and "opensta_prev.log" is the logfile I had when I ran the input command file.

s27.zip

Thanks

I found that attempting to run OpenSTA crashed immediately on a TCL error. By printing out the decoded string passed to Tcl_Eval(), I discovered that tcl/Splash.tcl procedure "show_warranty" has non-ASCII characters representing the double quotes around the term "AS IS". In effect, this effectively terminated the string at the non-ASCII component and the input to Tcl_Eval became bad syntax.

The very easy solution is to replace the non-ASCII characters with escaped ASCII quote characters.

I'm not sure what it is about my system (Fedora, perhaps, or maybe just the version of Tcl/Tk) causes the issue to show up, but it's definitely one of those cases where the ounce of prevention is worth the pound of cure.

---Tim

cmake option -DTCL_HEADER would appear not to be working because TCL_HEADER not included in STA_INCLUDE_DIRS in CMakeLists.txt. Possible fix in CMakeLists.txt is:

set(STA_INCLUDE_DIRS
app
dcalc
graph
liberty
network
parasitics
sdc
sdf
search
util
verilog
${CUDD_INCLUDE}
#Add Tcl header..
${TCL_HEADER}
)

You README.md says;

OpenSTA is dual licensed. It is released under GPL v3 as OpenSTA and is also licensed for commerical applications by Parallax Software without the GPL's requirements.

For this to be possible you need to require your contributors to sign a CLA with Parallax Software. However, I don't see anything in your README about this?

You can find out more information about CLAs at https://opensource.google.com/docs/cla/

Reference to missing proc at:
tcl/Power.tcl:250 set ports [get_pins_error "pins" $keys(-pins)]

Trying to use set_power_activity, but getting following error:

get_pins_error
invalid command name "get_pins_error"

First of all, congrats on a really great tool!

I had a minor niggle when timing the output of blocks synthesised with Yosys. Yosys inserts attributes into the verilog to indicate the source files used, typically something like
(* src multiplier.v:1 *)

OpenSTA does not recognise these, and so fails. OK, it's pretty straightforward to use awk or sed to remove these, so it's not a big problem. However, I did have a quick look in the lexer sources, and crowbar'ed the following into VerilogLex.ll, effectively creating another type of comment block.

%x ATTRIBUTE

"(*"	{ BEGIN ATTRIBUTE; }
<ATTRIBUTE>{
.

{EOL}	{ sta::verilog_reader->incrLine(); }

"*)"	{ BEGIN INITIAL; }

<<EOF>> {
	VerilogParse_error("unterminated attribute");
	BEGIN(INITIAL);
	yyterminate();
	}
}

Seems to work OK ..

Hi
I am trying to run a very small design using openSTA, and looks like it crashes at link_design with segmentation fault message. Can you please have a look?
Steps to reproduce the crash

1. Download testcase.tar.gz
2. tar -xvcf testcase.tar.gz
3. cd testcase
4. ./apps/sta -f map9v3.cmd

Hello,

there is an on-going effort to import OpenSTA in the OpenBSD port tree. Currently the main concern is related to the software license; even if it seems clear from all file headers that you are using the GPLv3, the "License" paragraph in README.md is confusing:

Copyright (c) 2019, Parallax Software, Inc. All rights reserved.

No part of this document may be copied, transmitted or disclosed in any form or fashion without the express written consent of Parallax Software, Inc.

Could you please clarify? Does your software integrally adhere to the GPL?

Thanks and regards

--
Alessandro

Hi,

I am unable to read a verilog that has "{" used for multi-assignment e.g.:

assign { 5865[8:2], 5865[0] } = { 5861[8:2], 5861[0] };

Errors while using read_verilog :

% read_verilog netlist.v
Error: netlist.v, line 7619 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39379 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39380 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39383 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39587 syntax error, unexpected '{', expecting ID.
Error: netlist.v, line 39612 syntax error, unexpected '{', expecting ID.

Can you please help me figure out if I am doing some mistake or this is actually a bug ?
Thanks in Advance

OpenSTA crashes (segfault) when issuing report_power

The behaviour varies with the commit version. It occurs with commit e2dd765, (as at 21/06/2019)

does not occur with a version I downloaded from master.zip on 18/06/19

does occur with a version from around (25/05/19)

does not occur with a version from around (29/01/19)

.. all the various versions are due to the fact that I am using docker images, and when building a docker image for other platforms, I pull the master.zip file from github (I should probably rethink my strategy!)

I'm having a problem pinning the versions down to a specific commit - is the commit number in a string anywhere in the code?

Hi,
I have a module with clock division inside, and i want to specify the output delays wrt the source clock instead of the generated one.

The sdc file is the following:

create_clock [get_ports CLK]  -name CLK  -period 2

create_generated_clock -name CLK_DIV -source CLK -divide_by 2 _5_/Q

set_input_delay -clock CLK  -max 0.5  [get_ports DATA_IN]
set_input_delay -clock CLK  -min 0  [get_ports DATA_IN]

#DATA1_OUT is starting from CLK
set_output_delay -clock CLK  -max 1  [get_ports DATA1_OUT]
set_output_delay -clock CLK  -min 0  [get_ports DATA1_OUT]

#DATA2_OUT is actually starting from CLK_DIV internally, but i want to specify the delay wrt source CLK
set_output_delay -clock CLK  -max 1  [get_ports DATA2_OUT]
set_output_delay -clock CLK  -min 0  [get_ports DATA2_OUT]

I then have the following report_checks:

[...]
Startpoint: _3_ (rising edge-triggered flip-flop clocked by CLK_DIV)
Endpoint: DATA2_OUT (output port clocked by CLK)
Path Group: CLK
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock CLK_DIV (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _3_/CK (DFFR_X1)
   0.10    0.10 ^ _3_/Q (DFFR_X1)
   0.00    0.10 ^ DATA2_OUT (out)
           0.10   data arrival time

   2.00    2.00   clock CLK (rise edge)
   0.00    2.00   clock network delay (ideal)
   0.00    2.00   clock reconvergence pessimism
  -1.00    1.00   output external delay
           1.00   data required time
---------------------------------------------------------
           1.00   data required time
          -0.10   data arrival time
---------------------------------------------------------
           0.90   slack (MET)

So OpenSTA looks to understand that the path is starting from a flip-flop clocked by CLK_DIV, but that i want to calculate the delay wrt to CLK. But the delay between CLK and CLK_DIV is not considered (so the DFF _5_ clock_to_Q delay).
How can i have it taken into account in the path check ?

If you need a test case, i ran this using nangate45 library and openroad-flow (at master branch commit 660fdb4):
testcase_genclock.zip

Thank you

Hello,
I am trying to install OpenSTA in "standalone" mode. I wanted to use cmake, but the link provided in the "Installing with CMake" subsection is dead:

$ git clone https://xp-dev.com/git/opensta
Cloning into 'opensta'...
fatal: repository 'https://xp-dev.com/git/opensta/' not found

OpenSTA segfaults on any cell in the netlist that has no pins.
I found a fix for this that (so far) seems to work: In VerilogReader.cc before line 930 (first line of VerilogModuleInst::namedPins()) add the following line:

if (!pins_) return false;

That seems to keep things happy.

---Tim

When you specify the units in the SDC file (say in ns for time) and the library is in (ps), the output of the write_sdc command will write a clock as 5ps instead of 5ns (because it doesn't output the units or scale the information correctly).

One possible solution is to simply write the units used to the new SDC file, so ensure there is no loss of information.
I've created a patch that writes a section the output SDC file to address this issue:
OpenSTA-writeunits.zip

Thanks,
Peter

Hello, James,
Like below source API shows, could you please point me to the source code of class like Pin or Instance?

Thanks!

Pin *
Network::findPin(const Instance *instance,
const LibertyPort *port) const
{
return findPin(instance, port->name());
}

Hi James,
In our memory libraries, we have below lines:
/* Library Documentation */
date : ".September xxxx"
revision : .x.x
comment : "Unit Area representation == xx.xxx sq.micron" ;

While reading these libraries, openSTA gives out below error while reading the "revision" keyword
line 42 syntax error, unexpected $undefined, expecting FLOAT or STRING or KEYWORD or '!'.

If I comment all above lines from library, openSTA works fine.
Do you think, its library syntax error (as mentioned in message) or openSTA interpretation issue?

[ 0%] Generating StaTclInitVar.cc
cd /cygdrive/e/Opensource/OpenSTA && etc/TclEncode.tcl /cygdrive/e/Opensource/OpenSTA/build_linux/StaTclInitVar.cc tcl_inits tcl/Util.tcl tcl/Graph.tcl tcl/Liberty.tcl tcl/Link.tcl tcl/Network.tcl tcl/NetworkEdit.tcl tcl/Sdc.tcl tcl/Search.tcl tcl/Cmds.tcl tcl/Variables.tcl tcl/Sta.tcl tcl/Power.tcl tcl/Splash.tcl dcalc/DelayCalc.tcl parasitics/Parasitics.tcl sdf/Sdf.tcl verilog/Verilog.tcl
": no such file or directoryog.tcl
while executing
"open $filename r"
(procedure "encode_file" line 2)
invoked from within
"encode_file $filename"
("foreach" body line 2)
invoked from within
"foreach filename $init_filenames {
encode_file $filename
}"
(file "etc/TclEncode.tcl" line 75)

make[2]: *** [CMakeFiles/OpenSTA.dir/build.make:102：StaTclInitVar.cc] 错误 1
make[2]: *** 正在删除文件“StaTclInitVar.cc”
make[2]: 离开目录“/cygdrive/e/Opensource/OpenSTA/build_linux”
make[1]: *** [CMakeFiles/Makefile2:159：CMakeFiles/OpenSTA.dir/all] 错误 2
make[1]: 离开目录“/cygdrive/e/Opensource/OpenSTA/build_linux”
make: *** [Makefile:153：all] 错误 2

Annotating sdf with -path seems not to work for hierarchical design. Issue seems to be in stringPrint in findPin in SdfReader. Possible fix shown below. Test case (hier.tar.gz) showing problem attached -- run without fix yields missing pin error messages, run with fix seems ok
hier_sdf.tar.gz
.

Pin *
SdfReader::findPin(const char *name)
{
if (path_) {
string path_name;
// original code, path name not used..
// stringPrint(path_name, path_, divider_, name);
//AF: Bug fix: include path hierarchy in name..
stringPrint(path_name, "%s%c%s",path_, divider_, name);
Pin *pin = network_->findPin(path_name.c_str());
return pin;
}
else
return network_->findPin(name);
}

Hi James
After reading parasitics, I get below opensta warning
opensta warning:
Warning: /home/anaghavsd/Desktop/work/to_kunal/mkSoc_wrapper.post_route.spef.max, line 1757581 net U1/lv_result__h66626[5] not found.

But when debugged more in SPEF file I see below:
Inside SPEF File:
*2233 U1/lv_result__h66626[5]

Line no. 1757581 78 *143:55 *2233:13 0.1392269

*D_NET *2233 4.270612

*CONN
*I *2234:Z O *L 0.0 *D dl03d1 *C 664.895 5310.3
*I *2235:A1 I *L 4.929 *C 668.2 5299.12
*N *2233:3 *C 664.28 5312.0
*N *2233:4 *C 664.28 5312.0
*N *2233:5 *C 664.28 5310.84
*N *2233:6 *C 664.28 5310.84
*N *2233:7 *C 666.52 5310.84
*N *2233:8 *C 666.52 5310.84
*N *2233:9 *C 666.52 5300.28
*N *2233:10 *C 666.52 5300.28
*N *2233:11 *C 668.2 5300.28
*N *2233:12 *C 668.2 5300.28
*N *2233:13 *C 668.2 5299.12

*CAP
1 *2234:Z 0.06939172
2 *2235:A1 0.0
3 *2233:3 0.1211474
4 *2233:4 0.06939172
5 *2233:5 0.2014812
6 *2233:6 0.1211474
7 *2233:7 0.2014812
8 *2233:8 0.6075613
9 *2233:9 0.2244984
10 *2233:10 0.6075613
11 *2233:11 0.2244984
12 *2233:12 0.101769
13 *2233:13 0.101769
14 *2233:12 *143:55 0.1392269
15 *2233:13 *143:55 0.1392269
16 *2233:8 *650420:9 0.4570534
17 *2233:10 *650420:9 0.4570534
18 *2233:8 *650438:264 0.0314983
19 *2233:10 *650438:264 0.0314983
20 *2233:10 *650438:263 0.03416146
21 *2233:10 *650438:265 0.09252438
22 *2233:3 *650438:264 0.1183352

*RES
1 *2233:3 *2233:4 6.000001
2 *2233:5 *2233:6 6.000001
3 *2233:7 *2233:8 6.000001
4 *2233:9 *2233:10 6.000001
5 *2233:11 *2233:12 6.000001
6 *2233:13 *2235:A1 6.000001
7 *2233:4 *2234:Z 0.1885714
8 *2233:6 *2233:3 0.4400001
9 *2233:10 *2233:8 3.125714
10 *2233:13 *2233:12 0.4400001
11 *2233:5 *2233:7 0.7485715
12 *2233:9 *2233:11 0.5885715

Opensta timing reports
After loading the verilog, when I use the below commands, I do see the net. So where is the net not found? Am I missing anything?
% get_nets U1/lv_result__h66626[5]
60ace52700000000_p_Net
% report_checks -digits 4 -fields {capacitance transition_time input_pins nets fanout} -no_line_splits -path_delay max -through [get_nets U1/lv_result__h66626[5] ]
Startpoint: U1/dma_dma_ccr_5_reg_16 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: U1/dma_rg_cpa_5_reg_5_ (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: max

Fanout        Cap       Slew      Delay       Time   Description

                                 0.0000     0.0000   clock CLK (rise edge)              
                                 6.7393     6.7393   clock network delay (propagated)   
                      0.3830     0.0000     6.7393 ^ U1/dma_dma_ccr_5_reg_16_/CP (sdnrb1)
                      0.0788     0.5712     7.3104 v U1/dma_dma_ccr_5_reg_16_/Q (sdnrb1)
     1     0.0063                                    U1/MUX_dma_m_xactor_f_rd_addr_enq_1__VAL_6_22 (net)
                      0.0788     0.0001     7.3106 v U1/U7585/I (buffd3)                
                      0.0839     0.2168     7.5274 v U1/U7585/Z (buffd3)                
     1     0.0081                                    U1/n744 (net)                      
                      0.0839     0.0002     7.5276 v U1/U78812/I (bufbd4)               
                      0.0707     0.1681     7.6956 v U1/U78812/Z (bufbd4)               
     1     0.0090                                    U1/n83296 (net)                    
                      0.0707     0.0002     7.6958 v U1/U78466/I (buffd7)               
                      0.0697     0.1758     7.8716 v U1/U78466/Z (buffd7)               
     2     0.0150                                    U1/n82946 (net)                    
                      0.0697     0.0003     7.8719 v U1/U54722/I (bufbd3)               
                      0.0805     0.1445     8.0164 v U1/U54722/Z (bufbd3)               
     2     0.0209                                    U1/n58764 (net)                    
                      0.0805     0.0004     8.0169 v U1/U96990/I (buffd1)               
                      0.3433     0.3475     8.3643 v U1/U96990/Z (buffd1)               
     7     0.0577                                    U1/n102366 (net)                   
                      0.3433     0.0016     8.3660 v U1/DP_OP_3952J2_127_2298/U167/I (buffd1)
                      0.0853     0.2665     8.6325 v U1/DP_OP_3952J2_127_2298/U167/Z (buffd1)
     1     0.0048                                    U1/DP_OP_3952J2_127_2298/n248 (net)
                      0.0853     0.0001     8.6326 v U1/DP_OP_3952J2_127_2298/U279/I (dl01d2)
                      0.1525     0.5225     9.1551 v U1/DP_OP_3952J2_127_2298/U279/Z (dl01d2)
     1     0.0057                                    U1/DP_OP_3952J2_127_2298/n142 (net)
                      0.1525     0.0001     9.1552 v U1/DP_OP_3952J2_127_2298/U280/I (dl01d2)
                      0.1497     0.5333     9.6885 v U1/DP_OP_3952J2_127_2298/U280/Z (dl01d2)
     1     0.0052                                    U1/DP_OP_3952J2_127_2298/n143 (net)
                      0.1497     0.0001     9.6886 v U1/DP_OP_3952J2_127_2298/U755/A2 (nr02d0)
                      0.8731     0.4852    10.1737 ^ U1/DP_OP_3952J2_127_2298/U755/ZN (nr02d0)
     1     0.0149                                    U1/DP_OP_3952J2_127_2298/n671 (net)
                      0.8731     0.0004    10.1742 ^ U1/DP_OP_3952J2_127_2298/U119/I (dl01d1)
                      0.2248     0.7421    10.9163 ^ U1/DP_OP_3952J2_127_2298/U119/Z (dl01d1)
     2     0.0121                                    U1/DP_OP_3952J2_127_2298/n138 (net)
                      0.2248     0.0004    10.9167 ^ U1/DP_OP_3952J2_127_2298/U649/A2 (an12d1)
                      0.3693     0.2971    11.2137 ^ U1/DP_OP_3952J2_127_2298/U649/Z (an12d1)
     2     0.0300                                    U1/DP_OP_3952J2_127_2298/n669 (net)
                      0.3694     0.0013    11.2150 ^ U1/DP_OP_3952J2_127_2298/U643/A2 (nd02d0)
                      0.3339     0.2181    11.4331 v U1/DP_OP_3952J2_127_2298/U643/ZN (nd02d0)
     3     0.0128                                    U1/DP_OP_3952J2_127_2298/n673 (net)
                      0.3339     0.0002    11.4333 v U1/DP_OP_3952J2_127_2298/U555/I (inv0d1)
                      0.1413     0.1331    11.5664 ^ U1/DP_OP_3952J2_127_2298/U555/ZN (inv0d1)
     1     0.0054                                    U1/DP_OP_3952J2_127_2298/n678 (net)
                      0.1413     0.0001    11.5665 ^ U1/DP_OP_3952J2_127_2298/U658/B2 (aoi21d1)
                      0.1942     0.1247    11.6912 v U1/DP_OP_3952J2_127_2298/U658/ZN (aoi21d1)
     2     0.0133                                    U1/DP_OP_3952J2_127_2298/n686 (net)
                      0.1942     0.0003    11.6915 v U1/DP_OP_3952J2_127_2298/U667/B1 (oai21d1)
                      0.8122     0.4559    12.1474 ^ U1/DP_OP_3952J2_127_2298/U667/ZN (oai21d1)
     2     0.0200                                    U1/DP_OP_3952J2_127_2298/n710 (net)
                      0.8122     0.0009    12.1483 ^ U1/DP_OP_3952J2_127_2298/U684/B1 (aoi21d2)
                      0.1328     0.3757    12.5240 v U1/DP_OP_3952J2_127_2298/U684/ZN (aoi21d2)
     2     0.0327                                    U1/DP_OP_3952J2_127_2298/n758 (net)
                      0.1328     0.0013    12.5253 v U1/DP_OP_3952J2_127_2298/U685/I (inv0d2)
                      0.1592     0.1115    12.6369 ^ U1/DP_OP_3952J2_127_2298/U685/ZN (inv0d2)
     3     0.0225                                    U1/DP_OP_3952J2_127_2298/n730 (net)
                      0.1592     0.0005    12.6374 ^ U1/DP_OP_3952J2_127_2298/U690/A1 (xn02d1)
                      0.1289     0.2710    12.9085 v U1/DP_OP_3952J2_127_2298/U690/ZN (xn02d1)
     1     0.0084                                    U1/DP_OP_3952J2_127_2298/n32 (net) 
                      0.1289     0.0002    12.9086 v U1/DP_OP_3952J2_127_2298/U23/I (buffd1)
                      0.0917     0.2155    13.1242 v U1/DP_OP_3952J2_127_2298/U23/Z (buffd1)
     1     0.0060                                    U1/DP_OP_3952J2_127_2298/n231 (net)
                      0.0917     0.0001    13.1243 v U1/DP_OP_3952J2_127_2298/U124/I (dl03d1)
                      0.3833     2.3981    15.5224 v U1/DP_OP_3952J2_127_2298/U124/Z (dl03d1)
     1     0.0030                                    **U1/lv_result__h66626[5]** (net)      
                      0.3833     0.0000    15.5224 v U1/U26534/A1 (aor22d1)             
                      0.1082     0.2456    15.7680 v U1/U26534/Z (aor22d1)              
     1     0.0073                                    U1/n5537 (net)                     
                      0.1082     0.0002    15.7681 v U1/dma_rg_cpa_5_reg_5__U3/I0 (mx02d4)
                      0.1199     0.3415    16.1096 v U1/dma_rg_cpa_5_reg_5__U3/Z (mx02d4)
     1     0.0074                                    U1/n23827 (net)                    
                      0.1199     0.0001    16.1098 v U1/U78973/I (dl03d1)               
                      0.4280     2.4393    18.5490 v U1/U78973/Z (dl03d1)               
     1     0.0049                                    U1/n83458 (net)                    
                      0.4280     0.0000    18.5490 v U1/U119807/I (bufbd4)              
                      0.0775     0.2558    18.8048 v U1/U119807/Z (bufbd4)              
     1     0.0118                                    U1/n119222 (net)                   
                      0.0775     0.0002    18.8050 v U1/U119809/I (buffd2)              
                      0.0611     0.1311    18.9362 v U1/U119809/Z (buffd2)              
     1     0.0053                                    U1/n119224 (net)                   
                      0.0611     0.0001    18.9363 v U1/U119808/I (buffd3)              
                      0.0733     0.2024    19.1387 v U1/U119808/Z (buffd3)              
     1     0.0033                                    U1/n119223 (net)                   
                      0.0733     0.0001    19.1388 v U1/dma_rg_cpa_5_reg_5_/D (sdnrb1)  
                                           19.1388   data arrival time                  

                                20.0000    20.0000   clock CLK (rise edge)              
                                 6.7002    26.7002   clock network delay (propagated)   
                                -0.9000    25.8002   clock uncertainty                  
                                 0.0000    25.8002   clock reconvergence pessimism      
                                           25.8002 ^ U1/dma_rg_cpa_5_reg_5_/CP (sdnrb1) 
                                -0.4036    25.3966   library setup time                 
                                           25.3966   data required time                 

                                           25.3966   data required time                 
                                          -19.1388   data arrival time                  

                                            6.2578   slack (MET)                        

Hi James,
When I tried to install OpenSTA and executed $ ./bootstrap , I got the error messages below:

aclocal: couldn't open directory `m4': No such file or directory
autoreconf: aclocal failed with exit status: 1

After I create a directory named m4 by $ mkdir -p m4, the issue is solved.

Hi
In some of our constraints file, we have below constraint

1. set_input_transition -clock clk -min -rise 102 [get_ports mem_rdata_0_ ]

But instead, openSTA uses below
2) set_input_transition -min -rise 102 [get_ports mem_rdata_0_ ]

While using 1) OpenSTA gives an error that -clock option not supported. Any reason?
We wanted to keep consistent SDC constraints across different tools for benchmarking and evaluation. Can you please let know your thoughts?

Hi James
I will be writing blog and submitting paper at DAC (not sure if it will be accepted, but my last year paper was accepted and had got good inflow of crowd)
My paper will be on opensta bench-marking and correlation results (with other tools), that we achieved on a major RISC-V processor using pre-layout and post-layout netlist.
Do you mind if I put your name under acknowledgements in blog and in DAC?
A sample is shown below:
https://www.vlsisystemdesign.com/wp-content/uploads/2017/10/conference_poster_6.pdf

Hi,
I wrote the following constraint.sdc for gcd example (nangate45):

create_clock [get_ports clk]  -name core_clock  -period 2

#set output delay for all
set_output_delay -clock core_clock -max 1 [all_outputs]
set_output_delay -clock core_clock -min 0 [all_outputs]

#except for one...
unset_output_delay [get_ports resp_val]
set_output_delay -clock core_clock -max 0.5 [get_ports resp_val]
set_output_delay -clock core_clock -min 0   [get_ports resp_val]

When running opensta, I receive the following error :
...
Error: unset_output_delay requires two positional arguments.
number instances in verilog is 272
...

I also tried (even though it is marked as optional in the manual)

unset_output_delay -clock core_clock [get_ports resp_val]

but same response.
What am i missing ?
Thanks,
Quentin

Hello,
Currently using the OpenROAD flow but I get a warning during the STA Placement step:

OpenSTA Copyright (c) 2018, Parallax Software, Inc.
License GPLv3: GNU GPL version 3 http://gnu.org/licenses/gpl.html

This is free software, and you are free to change and redistribute it
under certain conditions; type show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type show_warranty'.
INFO: Now linking: grid_clb
INFO: Successfully linked: grid_clb
Warning: , line 1 net grid_clb_0_\/fle_2__ff_phy_1__D_0_ not found.

My Verilog was a structural Verilog design which I fed into Synopsys DC in order to get a flat design.
As such, many net names have "/" in their name. I replaced those by underscore and it seems to alleviate the issue. Is the parser not capable of dealing with "/" characters?

Sigh - I found the -x command line argument quite useful. I used to use it to construct an sta call from variables in my make file.

Now I have to first of all create a command script, and then invoke sta with that script (not forgetting -exit of course .. as if I would ..)

In my dreams, I would have a '-x' argument that worked multiple times, so that I could do something like

sta -exit > report-file \
-x "read_liberty -max ${SYNTH.EARLY.LIB}" \
-x "read_liberty -min ${SYNTH.LATE.LIB}" \
-x "read_verilog ${VLOG.GATE.NET}" \
-x "link_design ${VLOG.GATE.TOP}" \
-x "report_checks"

.. where SYNTH.EARLY.LIB is a make variable, set elsewhere. Yosys has an argument like this, the -p option.

Of course, I can survive without this using a script generation technique, so it's not a showstopper.